HYB18T512160AF INFINEON [Infineon Technologies AG], HYB18T512160AF Datasheet - Page 29

• Manufacturer Part Number: HYB18T512160AF
• Description: 512-Mbit DDR2 SDRAM
• Manufacturer: INFINEON [Infineon Technologies AG]

3.4
For application flexibility, burst length, burst type, CAS
latency, DLL reset function, write recovery time (WR)
are user defined variables and must be programmed
with
Additionally, DLL disable function, additive CAS
latency, driver impedance, On Die Termination (ODT),
single-ended strobe and Off Chip Driver impedance
adjustment (OCD) are also user defined variables and
must be programmed with an Extended Mode Register
Set (EMRS) command.
Contents of the Mode Register (MR) or Extended Mode
Registers (EMR(1, 2, 3)) can be altered by re-executing
the MRS and EMRS Commands. If the user chooses to
modify only a subset of the MR or EMR variables, all
variables must be redefined when the MRS or EMRS
commands are issued.
After initial power up, all MRS and EMRS Commands
must be issued before read or write cycles may begin.
3.5
The mode register stores the data for controlling the
various operating modes of DDR2 SDRAM. It programs
CAS latency, burst length, burst sequence, test mode,
DLL reset, Write Recovery (WR) and various vendor
specific options to make DDR2 SDRAM useful for
various applications.
The default value of the mode register is not defined,
therefore the mode register must be written after
power-up for proper operation. The mode register is
written by asserting low on CS, RAS, CAS, WE,
BA[1:0], while controlling the state of address pins
A[13:0]. The DDR2 SDRAM should be in all bank
precharged (idle) mode with CKE already high prior to
writing into the mode register. The mode register set
command cycle time (tMRD) is required to complete
the write operation to the mode register. The mode
register contents can be changed using the same
Data Sheet
a
Mode
Programming the Mode Register and Extended Mode Registers
DDR2 SDRAM Mode Register Set (MRS)
Register
Set
(MRS)
command.
29
All banks must be in a precharged state and CKE must
be high at least one cycle before the Mode Register Set
Command can be issued. Either MRS or EMRS
Commands are activated by the low signals of CS,
RAS, CAS and WE at the positive edge of the clock.
When both bank addresses BA[1:0] are 0, the DDR2
SDRAM enables the MRS command. When the bank
addresses BA0 is 1 and BA1is 0, the DDR2 SDRAM
enables the EMRS(1) command.
The address input data during this cycle defines the
parameters to be set as shown in the MRS and EMRS
tables. A new command may be issued after the mode
register set command cycle time (t
MRS, EMRS and DLL Reset do not affect array
contents, which means reinitialization including those
can be executed any time after power-up without
affecting array contents.
command and clock cycle requirements during normal
operation as long as all banks are in the precharged
state. The mode register is divided into various fields
depending on functionality.
Burst length is defined by A[2:0] with options of 4 and 8
bit burst length. Burst address sequence type is defined
by A3 and CAS latency is defined by A[6:4]. A7 is used
for test mode and must be set to 0 for normal DRAM
operation. A8 is used for DLL reset. A[11:9] are used for
write recovery time (WR) definition for Auto-Precharge
mode. With address bit A12 two Power-Down modes
can be selected, a “standard mode” and a “low-power”
Power-Down mode, where the DLL is disabled.
Address bit A13 and all “higher” address bits have to
be set to 0 for compatibility with other DDR2 memory
products with higher memory densities.
HYB18T512[40/80/16]0AF–[3/3S/3.7/5]
512-Mbit DDR2 SDRAM
Functional Description
09112003-SDM9-IQ3P
MRD
Rev. 1.3, 2005-01
).