HYB18T512160AF INFINEON [Infineon Technologies AG], HYB18T512160AF Datasheet - Page 98

• Manufacturer Part Number: HYB18T512160AF
• Description: 512-Mbit DDR2 SDRAM
• Manufacturer: INFINEON [Infineon Technologies AG]

1) Timings are guaranteed with CK/CK differential Slew Rate of 2.0 V/ns. For DQS signals timings are guaranteed with a
2) The CK/CK input reference level (for timing reference to CK/CK) is the point at which CK and CK cross. The DQS/DQS,
3) Inputs are not recognized as valid until
4) The output timing reference voltage level is
5)
7.2
Table 53
Parameter
DQ output access time from CK / CK
CAS A to CAS B command period
CK, CK high-level width
CKE minimum high and low pulse width
CK, CK low-level width
Auto-Precharge write recovery + precharge time
Minimum time clocks remain ON after CKE
asynchronously drops LOW
DQ and DM input hold time (differential data strobe)
DQ and DM input pulse width (each input)
DQS output access time from CK / CK
DQS input low (high) pulse width (write cycle)
DQS-DQ skew (for DQS & associated DQ signals)
Write command to 1st DQS latching transition
DQ and DM input setup time (differential data strobe)
DQS falling edge hold time from CK (write cycle)
DQS falling edge to CK setup time (write cycle)
Clock half period
Data-out high-impedance time from CK / CK
Address and control input hold time
Address and control input pulse width
(each input)
Address and control input setup time
DQ low-impedance time from CK / CK
DQS low-impedance from CK / CK
Mode register set command cycle time
OCD drive mode output delay
Data Sheet
differential Slew Rate of 2.0 V/ns in differential strobe mode and a Slew Rate of 1 V/ns in single ended mode. For other
Slew Rates see Chapter 8. Timings are further guaranteed for normal OCD drive strength (EMRS(1) A1 = 0) under the
“Reference Load for Timing Measurements” according to Chapter 8.1 only.
RDQS/RDQS, input reference level is the crosspoint when in differential strobe mode; The input reference level for signals
other than CK/CK, DQS/DQS, RDQS/RDQS is defined in Chapter 8.3.
recognized as low.
t
equal to 9 x
RAS.MAX
is calculated from the maximum amount of time a DDR2 device can operate without a refresh command which is
AC Timing Parameters
Timing Parameter by Speed Grade - DDR2-667
t
REFI
.
V
REF
V
stabilizes. During the period before
TT
. See section 8 for the reference load for timing measurements.
98
Symbol
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
AC
CCD
CH
CKE
CL
DAL
DELAY
DH
DIPW
DQSCK
DQSL,H
DQSQ
DQSS
DS
DSH
DSS
HP
HZ
IH
IPW
IS
LZ(DQ)
LZ(DQS)
MRD
OIT
(base)
(base)
(base)
(base)
HYB18T512[40/80/16]0AF–[3/3S/3.7/5]
DDR2-667
Min.
–450
2
0.45
3
0.45
WR +
t
175
0.35
–400
0.35
240
– 0.25
100
0.2
0.2
MIN. (
—
275
0.6
200
2
t
2
0
IS
AC.MIN
x
+
t
AC.MIN
t
V
CK
REF
t
t
CL,
RP
+
stabilizes, CKE = 0.2 x
t
t
CH
IH
512-Mbit DDR2 SDRAM
)
Electrical Characteristics
Max.
+450
—
0.55
—
0.55
—
––
––
—
—
—
+ 0.25
—
—
—
t
—
—
—
t
t
—
12
AC.MAX
AC.MAX
AC.MAX
400
09112003-SDM9-IQ3P
Rev. 1.3, 2005-01
Unit
ps
t
t
t
t
t
ns
ps
t
ps
t
ps
t
ps
t
t
ps
ps
t
ps
ps
ps
t
ns
CK
CK
CK
CK
CK
CK
CK
CK
CK
CK
CK
CK
V
DDQ
Note
1)2)3)4)5)6)
7)
8)
9)
10)
9)
11)
12)
9)
9)
12)
12)
is