IBM25PPC440GP IBM Microelectronics, IBM25PPC440GP Datasheet - Page 43

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IBM25PPC440GP

Manufacturer Part Number
IBM25PPC440GP
Description
PowerPC 440GP Embedded Processor
Manufacturer
IBM Microelectronics
Datasheet
PowerPC 440GP Embedded Processor Data Sheet
Signal Functional Description
Notes:
1. Receiver input has hysteresis
2. Must pull up (recommended value is 3kΩ to 3.3V, 10kΩ to 5V)
3. Must pull down (recommended value is 1kΩ)
4. If not used, must pull up (recommended value is 3kΩ to 3.3V)
5. If not used, must pull down (recommended value is 1kΩ)
6. Strapping input during reset; pull-up or pull-down required
5/13/04
PCIXReset
PCIXSErr
PCIXStop
PCIXTRDY
DDR SDRAM Interface
BA0:1
BankSel0:3
CAS
ClkEn0:3
DM0:8
DQS0:8
ECC0:7
MemAddr00:12
MemClkOut0
MemClkOut0
MemData00:63
MemVRef1:2
RAS
WE
Ethernet Interface
EMCCD,
EMC1RxErr
EMCCrS,
EMC0CrSDV
EMCMDClk
EMCMDIO
Signal Name
Brings PCI device registers and logic to a consistent
state.
Reports address parity errors, data parity errors on the
Special Cycle command, or other catastrophic system
errors.
Indicates the current target is requesting the master to
stop the current transaction.
I
current data phase of the transaction.
Bank Address supporting up to four internal banks.
Selects up to four external DDR SDRAM banks.
Column Address Strobe.
Clock Enable. One for each bank.
Memory write data byte lane masks. MEMDM8 is the
byte lane mask for the ECC byte lane.
Byte lane data strobe. DQS8 is the data strobe for the
ECC byte lane.
ECC check bits 0:7.
Memory address bus.
Subsystem clock.
Memory data bus.
Memory reference voltage (SV
Row Address Strobe.
Write Enable.
MII: Collision detection
RMII 1: Receive error
MII: Carrier sense
RMII 0: Carrier sense data valid
MII and RMII: Management data clock
MII and RMII: Transfer command and status information
between MII and PHY
ndicates the target agent’s ability to complete the
(Part 2 of 7)
Description
REF
) input.
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
O
O
O
O
O
O
O
O
O
O
O
I
2.5V SSTL_2
2.5V SSTL_2
2.5V SSTL_2
2.5V SSTL_2
2.5V SSTL_2
2.5V SSTL_2
2.5V SSTL_2
2.5V SSTL_2
2.5V SSTL_2
2.5V SSTL_2
2.5V SSTL_2
2.5V SSTL_2
3.3V LVTTL
3.3V LVTTL
3.3V LVTTL
3.3V LVTTL
Voltage Ref
5V tolerant
5V tolerant
5V tolerant
5V tolerant
3.3V PCI
3.3V PCI
3.3V PCI
3.3V PCI
Receiver
Type
Page 43 of 72
Notes
4
4
4

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