IBM25PPC440GP IBM Microelectronics, IBM25PPC440GP Datasheet - Page 59

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IBM25PPC440GP

Manufacturer Part Number
IBM25PPC440GP
Description
PowerPC 440GP Embedded Processor
Manufacturer
IBM Microelectronics
Datasheet
PowerPC 440GP Embedded Processor Data Sheet
I/O Specifications—All Speeds
Notes:
1. Ethernet interface meets timing requirements as defined by IEEE 802.3 standard.
2. PCI-X timings are for asynchronous operation up to 133MHz. PCI-X input setup time requirement is 1.2ns for 133MHz
3. The clock frequency for RMII operation is 50MHz ± 100ppm.
4. The clock frequency for SMII operation is 125MHz ± 100ppm.
5. These are DDR signals that can change on both the positive and negative clock transitions.
5/13/04
System Interface
SysClk
TmrClk
SysReset
Halt
SysErr
TestEn
DrvrInh1:2
GPIO00:31
Trace Interface
TrcClk
TrcBS0:2
TrcES0:4
TrcTS0:6
and 1.7ns for 66MHz. PCI timings (in parentheses) are for asynchronous operation up to 66MHz. PCI output hold time
requirement is 1ns for 66MHz and 2ns for 33MHz.
Signal
Setup Time
(T
IS
n/a
n/a
min)
Input (ns)
Hold Time
(T
IH
n/a
n/a
min)
(Part 3 of 3)
Valid Delay
(T
OV
n/a
n/a
n/a
n/a
n/a
max)
Output (ns)
Hold Time
(T
OH
n/a
n/a
n/a
n/a
n/a
min)
(minimum)
Output Current (mA)
I/O H
10.3
10.3
10.3
10.3
10.3
10.3
n/a
n/a
n/a
n/a
n/a
n/a
(minimum)
I/O L
n/a
n/a
n/a
n/a
7.1
n/a
n/a
7.1
7.1
7.1
7.1
7.1
Clock
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