IBM25PPC440GP IBM Microelectronics, IBM25PPC440GP Datasheet - Page 6

• Manufacturer Part Number: IBM25PPC440GP
• Description: PowerPC 440GP Embedded Processor
• Manufacturer: IBM Microelectronics

PPC440GP Functional Block Diagram
The PPC440GP is designed using the IBM Microelectronics Blue Logic
functional blocks are integrated together to create an application-specific product (ASIC). This approach
provides a consistent way to create complex ASICs using IBM CoreConnect Bus
Note: IBM CoreConnect buses provide:
Address Maps
The PPC440GP incorporates two address maps. The first is a fixed processor system memory address map.
This address map defines the possible contents of various address regions which the processor can access.
The second address map is for Device Configuration Registers (DCRs). The DCRs are accessed by software
running on the PPC440GP processor through the use of mtdcr and mfdcr instructions.
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45 internal
13 external
Controller
Universal
Interrupt
• 128-bit PLB interfaces up to 133.33MHz, 2.1GB/s
• 32-bit OPB interfaces up to 66.66MHz, 266MB/s
13-bit addr
32/64-bit data
133MHz max
Control
DDR SDRAM
Reset
Clock
D-Cache
Controller
32KB
JTAG
Processor Core
PPC440
133MHz max
Timers
MMU
PowerPC 440GP Embedded Processor Data Sheet
I-Cache
32KB
Trace
Power
Mgmt
Processor Local Bus (PLB)
Bridge
PCI-X
SRAM
8KB
Arb
DCR Bus
DCRs
(4-Channel)
Controller
DMA
Timers
On-chip Peripheral Bus (OPB)
GP
MAL
Bridge
OPB
™
GPIO
methodology in which major
Ethernet
x2
1 MII
or
2 RMII
or
2 SMII
™
IIC
x2
Architecture.
Controller
External
Bus
UART
x2
66MHz max
32-bit addr
32-bit data
Bus Master
Controller
External
5/13/04