IBM25PPC440GP IBM Microelectronics, IBM25PPC440GP Datasheet - Page 66

• Manufacturer Part Number: IBM25PPC440GP
• Description: PowerPC 440GP Embedded Processor
• Manufacturer: IBM Microelectronics

In operation, following the receipt of an address and read command from the PPC440GP, the SDRAM
generates data and the DQS signals coincident with MemClkOut0. The data is latched into the PPC440GP
using a DQS signal that is delayed 1/4 of a cycle. In order to accommodate timing variations introduced by
the system designs using this chip, the three-stage data path shown below is used to eliminate metastability
and allow data sampling to be adjusted for minimum latency. This adjustment requires programming the
Read Clock delay and the selection of Stage 1, Stage 2, or Stage 3 data for sampling at RDSP.
DDR SDRAM Read Data Path
I/O Timing—DDR SDRAM T
Notes:
1. T
2. T
3. Clock speed for the values in the table is 133MHz.
4. The time values for T
In the following examples, the data strobes (DQS) and the data are shown to be coincident. There is actually
a slight skew as specified by the SDRAM specifications, and there can be additional skew due to loading and
signal routing. It is recommended that the signal length for all of the eight DQS signals be matched.
Page 66 of 72
DQS
Data
SIN
DIN
Package pins
Signal Name
= Delay from DQS at package pin to C on Stage 1 FF.
= Delay from data at package pin to D on Stage 1 FF.
DQS0
DQS1
DQS2
DQS3
DQS4
DQS5
DQS6
DQS7
DQS8
PLB Clock
Cycle
Delay
1/4
D
Stage 1
FF,
XL
C
SIN
Q
minimum
Programmed
T
Read Clock
FF Timing:
include 1/4 of a cycle at 133MHz (7.5ns x 0.25 = 1.875 ns).
SIN
2.775
2.775
2.775
2.775
2.775
2.775
2.775
2.775
2.775
T
T
T
Delay
IS
IH
P
PowerPC 440GP Embedded Processor Data Sheet
(ns)
= Propagation delay (D to Q or C to Q) =
= Input setup time = 0.2ns
= Input hold time = 0.1ns
D
Stage 2
SIN
FF
C
and T
maximum
Q
T
SIN
3.775
3.775
3.775
3.775
3.775
3.775
3.775
3.775
3.775
(ns)
DIN
D
Stage 3
MemData00:07
MemData08:151
MemData16:23
MemData24:31
MemData32:39
MemData40:47
MemData48:55
MemData56:63
ECC0:7
FF
C
Signal Name
Q
0.6ns maximum
(SDRAM0_TR1)
Read Select
Mux
ECC
minimum
T
DIN
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
FF: Flip-Flop
XL: Transparent Latch
(ns)
D
RDSP
FF
C
Q
maximum
T
DIN
PLB bus
2.0
2.0
2.0
2.0
2.0
2.0
2.0
2.0
2.0
(ns)
5/13/04