IBM25PPC440GP IBM Microelectronics, IBM25PPC440GP Datasheet - Page 69

• Manufacturer Part Number: IBM25PPC440GP
• Description: PowerPC 440GP Embedded Processor
• Manufacturer: IBM Microelectronics

PowerPC 440GP Embedded Processor Data Sheet
Example 3:
In this example, ECC is enabled. This requires that Stage 3 data be sampled at (3). If ECC is disabled, the
system will still work, but there will be more latency before the data is sampled into RDSP. Again, T
and T
DDR SDRAM Read Cycle Timing—Example 3
5/13/04
Read Clock Delayed
Data in Stage 1 D
Data out Stage 1
Data out Stage 3
DQS Stage 1 C
Data in at RDSP
TE
Data out RDSP
Data out Stage 2
= 4.3ns at worst case conditions.
Data at pin
DQS at pin
PLB Clock
with ECC
with ECC
with ECC
T
DIN
High
Low
High
High
Low
Low
High
High
Low
Low
T
T
D0
SIN
T
T
P
TE
T
D0
= Propagation delay from Stage 2 input to RDSP input w/o ECC
= Propagation delay from Stage 2 input to RDSP input with ECC
D0
T
D1
P
D1
D0
D1
D2
D0
D2
D1
D2
D3
T
TE
D3
D2
D3
D0
D1
D2
D3
(3)
D0
D1
D2
D3
D0
D1
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D2
D3
T
= 1.5ns
D2
D3