IBM25PPC440GP IBM Microelectronics, IBM25PPC440GP Datasheet - Page 54
IBM25PPC440GP
Manufacturer Part Number
IBM25PPC440GP
Description
PowerPC 440GP Embedded Processor
Manufacturer
IBM Microelectronics
Datasheet
1.IBM25PPC440GP.pdf
(72 pages)
- Current page: 54 of 72
- Download datasheet (2Mb)
Spread Spectrum Clocking
Care must be taken when using a spread spectrum clock generator (SSCG) with the PPC440GP. This
controller uses a PLL for clock generation inside the chip. The accuracy with which the PLL follows the SSCG
is referred to as tracking skew. The PLL bandwidth and phase angle determine how much tracking skew
there is between the SSCG and the PLL for a given frequency deviation and modulation frequency. When
using an SSCG with the PPC440GP the following conditions must be met:
Notes:
Important: It is up to the system designer to ensure that any SSCG used with the PPC440GP meets the
Page 54 of 72
• The frequency deviation must not violate the minimum clock cycle time. Therefore, when operating the
• The maximum frequency deviation cannot exceed −3%, and the modulation frequency cannot exceed
• Use the Peripheral Bus Clock for logic that is synchronous to the peripheral bus since this clock tracks
• Use the DDR SDRAM MemClkOut since it also tracks the modulation.
PPC440GP with one or more internal clocks at their maximum supported frequency, the SSCG can only
lower the frequency.
40kHz. In some cases, on-board PPC440GP peripherals impose more stringent requirements.
the modulation.
1. The serial port baud rates are synchronous to the modulated clock. The serial port has a tolerance of
2. Ethernet operation is unaffected.
3. IIC operation is unaffected.
approximately 1.5% on baud rate before framing errors begin to occur. The 1.5% tolerance assumes
that the connected device is running at precise baud rates.
above requirements and does not adversely affect other aspects of the system.
PowerPC 440GP Embedded Processor Data Sheet
5/13/04
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