IBM25PPC440GP IBM Microelectronics, IBM25PPC440GP Datasheet - Page 63

• Manufacturer Part Number: IBM25PPC440GP
• Description: PowerPC 440GP Embedded Processor
• Manufacturer: IBM Microelectronics

PowerPC 440GP Embedded Processor Data Sheet
DDR SDRAM Write Operation
The following diagram illustrates the relationship among the signals involved with a DDR write operation.
DDR SDRAM Write Cycle Timing
5/13/04
MemClkOut0(90)
MemClkOut0
T
T
T
T
T
T
SA
HD
DS
HA
SD
SK
Addr/Cmd
MemData
PLB Clk
= Setup time for address and command signals to MemClkOut0(90)
= Delay from rising edge of MemClkOut0(0) to rising/falling edge of signal (skew)
= Setup time for data signals (minimum time data is valid before rising/falling edge of DSQ)
= Hold time for data signals (minimum time data is valid after rising/falling edge of DSQ)
= Delay from rising/falling edge of clock to the rising/falling edge of DQS
= Hold time for address and command signals from MemClkOut0(90)
DQS
T
SK
T
T
SA
HA
T
DS
T
SD
T
T
HD
DS
T
SD
T
HD
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