IBM25PPC440GP IBM Microelectronics, IBM25PPC440GP Datasheet - Page 68

• Manufacturer Part Number: IBM25PPC440GP
• Description: PowerPC 440GP Embedded Processor
• Manufacturer: IBM Microelectronics

Example 2:
In this example Read Clock is delayed almost 1/2 cycle. Without ECC, Stage 2 data can be sampled at (2). If
ECC is enabled, Stage 3 data must be sampled (see Example 3). In this example, T
4.3ns at worst case conditions.
DDR SDRAM Read Cycle Timing—Example 2
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Read Clock Delayed
Data out at RDSP
Data in Stage 1 D
Data out Stage 1
DQS Stage 1 C
Data in at RDSP
Data in at RDSP
Data out Stage 2
without ECC
without ECC
Data at pin
DQS at pin
PLB Clock
with ECC
T
DIN
High
Low
High
Low
High
Low
High
High
Low
Low
T
T
D0
SIN
T
T
P
TE
T
D0
PowerPC 440GP Embedded Processor Data Sheet
= Propagation delay from Stage 2 input to RDSP input w/o ECC
= Propagation delay from Stage 2 input to RDSP input with ECC
D0
T
D1
P
D1
D0
D1
T
T
T
D2
TE
D0
D2
D1
(2)
D2
D3
D0
D1
D3
D2
D3
D0
D1
D0
D1
D2
D3
D2
D3
T
= 1.5ns and T
D2
D3
D2
D3
TE
5/13/04
=