IBM25PPC440GP IBM Microelectronics, IBM25PPC440GP Datasheet - Page 9

• Manufacturer Part Number: IBM25PPC440GP
• Description: PowerPC 440GP Embedded Processor
• Manufacturer: IBM Microelectronics

PowerPC 440GP Embedded Processor Data Sheet
PowerPC 440 Processor Core
The PowerPC 440 processor core is designed for high-end applications: RAID controllers, routers, switches,
printers, set-top boxes, etc. It is the first processor core to implement the Book E PowerPC embedded
architecture and the first to use the 128-bit version of IBM’s on-chip CoreConnect Bus Architecture.
Features include:
Internal Buses
The PowerPC 440GP features three IBM standard on-chip buses: the Processor Local Bus (PLB), the On-
Chip Peripheral Bus (OPB), and the Device Control Register Bus (DCR). The high performance, high
bandwidth cores such as the PowerPC 440 processor core, the DDR SDRAM memory controller, and the
PCI-X bridge connect to the PLB. The OPB hosts lower data rate peripherals. The daisy-chained DCR
provides a lower bandwidth path for passing status and control information between the processor core and
the other on-chip cores.
Features include:
5/13/04
• Up to 500MHz operation
• PowerPC Book E architecture
• 32KB I-cache, 32KB D-cache
• Three logical regions in D-cache: locked, transient, normal
• D-cache full line flush capability
• 41-bit virtual address, 36-bit (64GB) physical address
• Superscalar, out-of-order execution
• 7-stage pipeline
• 3 execution pipelines
• Dynamic branch prediction
• Memory management unit
• Debug facilities
• 24 DSP instructions
• PLB
– 64-entry, full associative, unified TLB
– Separate instruction and data micro-TLBs
– Storage attributes for write-through, cache-inhibited, guarded, and big or little endian
– Multiple instruction and data range breakpoints
– Data value compare
– Single step, branch, and trap events
– Non-invasive real-time trace interface
– Single cycle multiply and multiply-accumulate
– 32 x 32 integer multiply
– 16 x 16 -> 32-bit MAC
– 128-bit implementation of the PLB architecture
– Separate and simultaneous read and write data paths
– 36-bit address
– Simultaneous control, address, and data phases
– Four levels of pipelining
– Byte enable capability supporting unaligned transfers
– 32- and 64-byte burst transfers
– 133MHz, maximum 4.2GB/s (simultaneous read and write)
– Processor:bus clock ratios of 3:1, 4:1, 5:1, 5:2, and 7:2
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