28F640W30 NUMONYX [Numonyx B.V], 28F640W30 Datasheet - Page 21

• Manufacturer Part Number: 28F640W30
• Description: Numonyx Wireless Flash Memory (W30)
• Manufacturer: NUMONYX [Numonyx B.V]

Numonyx™ Wireless Flash Memory (W30)
Table 6:
November 2007
Order Number: 290702-13
A[MAX:MIN]
P[2:1]-CS#
F[2:1]-OE#
F[3:1]-CE#
DQ[15:0]
Symbol
S-CS1#
R-OE#
F-WE#
S-CS2
Signal Descriptions - QUAD+ Package (Sheet 1 of 3)
Output
Input/
Type
Input
Input
Input
Input
Input
Input
Input
ADDRESS INPUTS: Inputs for all die addresses during read and write operations.
A0 is the lowest-order 16-bit wide address.
A[25:24] denote high-order addresses reserved for future flash device densities.
DATA INPUTS/OUTPUTS:
Data signals float when the flash device or its outputs are deselected. Data are internally latched
during writes on the flash device.
FLASH CHIP ENABLE: Low-true input.
F[3:1]-CE# low selects the associated flash memory die.
SRAM CHIP SELECT: Low-true / High-true input (S-CS1# / S-CS2 respectively).
S-CS1# and S-CS2 are available on stacked combinations with SRAM die and are RFU on stacked
combinations without SRAM die.
PSRAM CHIP SELECT: Low-true input.
FLASH OUTPUT ENABLE: Low-true input.
RAM OUTPUT ENABLE: Low-true input.
R-OE# is available on stacked combinations with PSRAM or SRAM die, and is an RFU on flash-only
stacked combinations.
FLASH WRITE ENABLE: Low-true input.
F-WE# controls writes to the selected flash die. Address and data are latched on the rising edge of
F-WE#.
• Inputs data and commands during write cycles.
• Outputs data during read cycles.
• When asserted, flash memory internal control logic, input buffers, decoders, and sense amplifiers
• When deasserted, the associated flash die is deselected, power is reduced to standby levels, and
• F1-CE# selects or deselects flash die #1.
• F2-CE# selects or deselects flash die #2 and is RFU on combinations with only one flash die.
• F3-CE# selects or deselects flash die #3 and is RFU on stacked combinations with only one or two
• When either/both SRAM Chip Select signals are asserted, SRAM internal control logic, input
• When either/both SRAM Chip Select signals are deasserted, the SRAM is deselected and its power
• When asserted, PSRAM internal control logic, input buffers, decoders, and sense amplifiers are
• When deasserted, the PSRAM is deselected and its power is reduced to standby levels.
• P1-CS# selects PSRAM die #1 and is available only on stacked combinations with PSRAM die. This
• P2-CS# selects PSRAM die #2 and is available only on stacked combinations with two PSRAM dies.
• Fx-OE# low enables the output buffers on the selected flash memory device.
• F[2:1]-OE# high disables the output buffers on the selected flash memory device, placing them in
• F1-OE# controls the outputs of flash die #1.
• F2-OE# controls the outputs of flash die #2 and flash die #3. F2-OE# is available on stacked
• R-OE# low enables the output buffers on the selected RAM.
• R-OE# high disables the RAM output buffers, and places the selected RAM outputs in High-Z.
• 128-Mbit Die : AMAX = A22
• 64-Mbit Die : AMAX = A21
• 32-Mbit Die : AMAX = A20
are active.
data and WAIT outputs are placed in high-Z state.
flash dies.
buffers, decoders, and sense amplifiers are active.
is reduced to standby levels.
active.
ball is an RFU on stacked combinations without PSRAM.
This ball is an RFU on stacked combinations without PSRAM or with a single PSRAM.
High-Z.
combinations with two or three flash die, and is RFU on stacked combinations with only one flash
die.
Description
Datasheet
21