28F640W30 NUMONYX [Numonyx B.V], 28F640W30 Datasheet - Page 49

• Manufacturer Part Number: 28F640W30
• Description: Numonyx Wireless Flash Memory (W30)
• Manufacturer: NUMONYX [Numonyx B.V]

Numonyx™ Wireless Flash Memory (W30)
Note:
9.1.2
9.1.3
November 2007
Order Number: 290702-13
Identifier codes, query data, and status register read operations execute as single-
synchronous or asynchronous read cycles. WAIT is asserted during these reads.
Access to the modes listed above is independent of V
places the flash device in a read mode. At initial power-up or after reset, the flash
device defaults to asynchronous read-array mode.
Asserting CE# enables flash device read operations. The flash device internally decodes
upper address inputs to determine which partition is accessed.
WE# and RST# must be deasserted during read operations.
If only asynchronous reads are to be performed in your system, CLK must be tied to a
valid V
Burst Suspend
The Burst Suspend feature allows the system to temporarily suspend a synchronous
burst operation if the system needs to use the flash device address and data bus for
other purposes. Burst accesses can be suspended during the initial latency (before data
is received) or after the flash device has output data. When a burst access is
suspended, internal array sensing continues and any previously latched internal data is
retained.
Burst Suspend occurs when CE# is asserted, the current address has been latched
(either ADV# rising edge or valid CLK edge), CLK is halted, and OE# is deasserted. CLK
can be halted when it is at V
and CLK is restarted. Subsequent CLK edges resume the burst sequence where it left
off.
Within the flash device, CE# gates the WAIT signal. Therefore, during Burst Suspend,
WAIT remains asserted and does not revert to a high-impedance state when OE# is
deasserted. This WAIT state can cause contention with another flash device attempting
to control the system READY signal during a Burst Suspend. System using the Burst
Suspend feature must not connect the flash device WAIT signal directly to the system
READY signal.
Refer to
Standby
De-asserting CE# deselects the flash device and places it in standby mode,
substantially reducing flash device power consumption. In standby mode, outputs are
placed in a high-impedance state independent of OE#. If deselected during a program
or erase algorithm, the flash device consumes active power until the program or erase
operation completes.
• Asserting ADV# opens the internal address latches.
• Asserting OE# activates the outputs, and gates the selected data onto the I/O bus.
• In asynchronous mode, the address is latched when ADV# is deasserted (when the
• In synchronous mode, the address is latched by either the rising edge of ADV# or
flash device is configured to use ADV#).
the rising (or falling) CLK edge while ADV# remains asserted, whichever occurs
first.
IH
Figure 15, “Burst Suspend” on page
level, the WAIT signal can be floated, and ADV# must be tied to ground.
IH
or V
IL
. To resume the burst access, OE# is reasserted
38.
PP
. An appropriate CUI command
Datasheet
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