28F640W30 NUMONYX [Numonyx B.V], 28F640W30 Datasheet - Page 22

• Manufacturer Part Number: 28F640W30
• Description: Numonyx Wireless Flash Memory (W30)
• Manufacturer: NUMONYX [Numonyx B.V]

Table 6:
Datasheet
22
Symbol
P-Mode,
F-RST#
F-VPEN
R-WE#
F-WP#
R-UB#
R-LB#
F-VPP,
ADV#
P-CRE
WAIT
CLK
Signal Descriptions - QUAD+ Package (Sheet 2 of 3)
Output
Power
Type
Input
Input
Input
Input
Input
Input
Input
RAM WRITE ENABLE: Low-true input.
R-WE# controls writes to the selected RAM die.
R-WE# is available on stacked combinations with PSRAM or SRAM die, and is an RFU on flash-only
stacked combinations.
CLOCK: Synchronizes the flash die with the system bus clock in synchronous read mode and
increments the internal address generator.
WAIT: Output signal.
Indicates invalid data during synchronous array or non-array flash memory reads. Read Configuration
Register bit 10 (RCR[10]) determines WAIT-asserted polarity (high or low). WAIT is High-Z if F-CE# is
deasserted; WAIT is not gated by F-OE#.
FLASH WRITE PROTECT: Low-true input.
F-WP# enables/disables the lock-down protection mechanism of the selected flash die.
ADDRESS VALID: Low-true input.
RAM UPPER / LOWER BYTE ENABLES: Low-true input.
During RAM read and write cycles:
R-UB# and R-LB# are available on stacked combinations with PSRAM or SRAM die, and are RFU on
flash-only stacked combinations.
FLASH RESET: Low-true input.
Exit from reset places the flash device in asynchronous read array mode.
P-Mode (PSRAM Mode): Low-true input.
P-Mode programs the Configuration Register, and enters/exits the Low Power Mode of the PSRAM die.
P-Mode is available on stacked combinations with asynchronous-only PSRAM die.
P-Mode, P-CRE is an RFU on stacked combinations without PSRAM die.
FLASH PROGRAM AND ERASE POWER: Valid F-V
device program/erase operations.
Flash memory array contents cannot be altered when F-V
erase / program operations at invalid F-V
F-VPEN (Erase/Program/Block Lock Enables) is not available for L18/L30 SCSP products.
• During synchronous read operations, addresses are latched on the rising edge of ADV#, or on the
• During asynchronous mode read operations, addresses are latched on the rising edge ADV#, or
• In synchronous array or non-array flash memory read modes, WAIT indicates invalid data when
• In asynchronous flash memory page read, and all flash memory write modes, WAIT is asserted.
• F-WP# low enables the lock-down mechanism where locked down blocks cannot be unlocked using
• F-WP# high disables the lock-down mechanism, allowing locked down blocks to be unlocked using
• During synchronous flash memory read operations, addresses are latched on the rising edge of
• During asynchronous flash memory read operations, addresses are latched on the rising edge of
• R-UB# low enables the RAM high order bytes on D[15:8].
• R-LB# low enables the RAM low-order bytes on D[7:0].
• F-RST# low initializes flash device internal circuitry and disables flash device operations.
• F-RST# high enables flash device operation.
• P-CRE (PSRAM Configuration Register Enable): High-true input.
• P-CRE is high, write operations load the Refresh Control Register or Bus Control Register.
• P-CRE applies only on combinations with synchronous PSRAM die.
next valid CLK edge with ADV# low, whichever occurs first.
are continuously flow-through when ADV# is kept asserted.
asserted and valid data when deasserted.
software commands.
software commands.
ADV#, or on the next valid CLK edge with ADV# low, whichever occurs first.
ADV#, or are continuously flow-through when ADV# is kept asserted.
PP
(F-V
Description
PEN
) voltages.
PP
voltage on this ball enables flash memory
Numonyx™ Wireless Flash Memory (W30)
Numonyx™ Wireless Flash Memory (W30)
PP
(F-V
PEN
) < V
PPLK
(V
Order Number: 290702-13
PENLK
). Do not attempt
November 2007