28F640W30 NUMONYX [Numonyx B.V], 28F640W30 Datasheet - Page 45

• Manufacturer Part Number: 28F640W30
• Description: Numonyx Wireless Flash Memory (W30)
• Manufacturer: NUMONYX [Numonyx B.V]

Numonyx™ Wireless Flash Memory (W30)
8.4.1
Note:
8.4.2
8.5
Note:
November 2007
Order Number: 290702-13
System Reset and RST#
The use of RST# during system reset is important with automated program/erase flash
devices, because the system expects to read from the flash memory when it comes out
of reset. If a CPU reset occurs without a flash memory reset, the CPU is not properly
initialized, because the flash memory might be providing status information instead of
array data.
To allow proper CPU/flash device initialization at system reset, connect RST# to the
system CPU RESET# signal.
System designers must guard against spurious writes when VCC voltages are above
V
signal to V
protection, because memory contents can be altered only after successful completion
of the two-step command sequences.
The flash device is also disabled until RST# is brought to V
input states.
By holding the flash device in reset (RST# connected to system PowerGood) during
power-up/down, invalid bus conditions during power-up can be masked, providing yet
another level of memory protection.
VCC, VPP, and RST# Transitions
The CUI latches commands issued by system software, and is not altered by VPP or
CE# transitions or WSM actions. Read-array mode is the power-up default state after
the flash device exits from reset mode or after VCC transitions above V
voltage).
After completing program or block erase operations (even after VPP transitions below
V
memory array access is desired.
Power Supply Decoupling
When the flash device is accessed, many internal conditions change. Circuits are
enabled to charge pumps and switch voltages. This internal activity produces transient
noise.
To minimize the effect of this transient noise, device decoupling capacitors are
required. Transient current magnitudes depend on the flash device output capacitive
and inductive loading. Two-line control and proper decoupling capacitor selection
suppresses these transient voltage peaks.
Each flash device must have a 0.1 µF ceramic capacitor connected between each power
(VCC, VCCQ, VPP)
inductance capacitors must be as close as possible to the package signals.
LKO
PPLK
. Because both WE# and CE# must be low for a command write, driving either
), the Read Array command must reset the CUI to read-array mode if flash
IH
inhibits writes to the flash device. The CUI architecture provides additional
,
and ground (VSS, VSSQ) signal. High-frequency, inherently low-
IH
, regardless of its control
LKO
(Lockout
Datasheet
45