28F640W30 NUMONYX [Numonyx B.V], 28F640W30 Datasheet - Page 79

• Manufacturer Part Number: 28F640W30
• Description: Numonyx Wireless Flash Memory (W30)
• Manufacturer: NUMONYX [Numonyx B.V]

Numonyx™ Wireless Flash Memory (W30)
14.0
Table 27: Read Configuration Register Definitions
Table 28: Read Configuration Register Descriptions (Sheet 1 of 2)
November 2007
Order Number: 290702-13
Read
Mod
13-11
RM
15
e
Bit
15
14
10
9
8
7
6
5
4
Res’d
14
R
Data Output Configuration
First Access Latency
WAIT Signal Polarity
WAIT Configuration
Burst Sequence
Set Read Configuration Register
The Set Read Configuration Register (RCR) command sets the burst order, frequency
configuration, burst length, and other parameters.
A two-bus cycle command sequence initiates this operation. The read configuration
register data is placed on the lower 16 bits of the address bus (A[15:0]) during both
bus cycles.
This command functions independently of the applied V
command, the flash device returns to read-array mode.
To examine the contents of the read configuration register, write the Read Identifier
command and then read location 05h. (See
Configuration
LC2
Read Mode
1. The Set Read Configuration Register command is written, along with the
2. A second write confirms the operation and again presents the read configuration
3. The read configuration register data is latched on the rising edge of ADV#, CE#, or
13
LC[2:0]
Latency Count
Name
Count
Clock
First Access
DOC
WC
RM
WP
configuration data (on the address bus).
register data on the address bus.
WE# (whichever occurs first).
CC
BS
R
R
R
LC1
12
LC0
11
0 = Synchronous Burst Reads Enabled
1 = Asynchronous Reads Enabled (Default)
Reserved
001 = Reserved
010 = Code 2
011 = Code 3
0 = WAIT signal is asserted low
1 = WAIT signal is asserted high (Default)
0 = Hold Data for One Clock
1 = Hold Data for Two Clock (Default)
0 = WAIT Asserted During Delay
1 = WAIT Asserted One Data Cycle before Delay (Default)
1 = Linear Burst Order (Default)
0 = Burst Starts and Data Output on Falling Clock Edge
1 = Burst Starts and Data Output on Rising Clock Edge (Default)
Reserved
Reserved
Polarit
WAIT
WP
10
y
Config
Outpu
Data
DOC
9
t
Confi
WAI
WC
T
g
8
t Seq
100 = Code 4
101 = Code 5
111 = Reserved (Default)
Burs
Description
BS
7
Table 27
Confi
Cloc
CC
k
g
6
1
and
Res’
d
R
5
PP
Table
voltage. After executing this
Res’
d
R
4
28.)
Burs
Wra
BW
p
3
t
BL2
2
Burst Length
BL1
1
Datasheet
Notes
2
5
3
5
5
6
6
6
,6
BL0
0
79