16F876 Microchip Technology, 16F876 Datasheet
16F876
Related parts for 16F876
16F876 Summary of contents
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... CMOS FLASH Microcontrollers Devices Included in this Data Sheet: • PIC16F873 • PIC16F876 • PIC16F874 • PIC16F877 Microcontroller Core Features: • High-performance RISC CPU • Only 35 single word instructions to learn • All single cycle instructions except for program branches which are two cycle • ...
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... RE2/CS/AN7 PIC16F877 PIC16F874 OSC1/CLKIN 14 OSC2/CLKOUT 15 RC0/T1OSO/T1CK1 RC0/T1OSO/T1CKI OSC2/CLKOUT 31 OSC1/CLKIN RE2/AN7/CS 27 RE1/AN6/WR 26 RE0/AN5/RD 25 RA5/AN4/ RA4/T0CKI 39 RB3/PGM 38 RB2 37 RB1 RB0/INT RD7/PSP7 32 RD6/PSP6 31 RD5/PSP5 30 RD4/PSP4 29 RC7/RX/DT 1999 Microchip Technology Inc. ...
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... MSSP, USART MSSP, USART MSSP, USART — PSP 5 input channels 8 input channels 5 input channels 35 Instructions 35 Instructions 35 Instructions PIC16F87X PIC16F876 PIC16F877 MHz MHz POR, BOR POR, BOR (PWRT, OST) (PWRT, OST 368 368 256 256 13 14 Ports A,B,C ...
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... However, we realize that we may have missed a few things. If you find any information that is missing or appears in error, please: • Fill out and mail in the reader response form in the back of this data sheet. • E-mail us at webmaster@microchip.com. We appreciate your assistance in making this a better document. DS30292B-page 4 To Our Valued Customers 1999 Microchip Technology Inc. ...
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... Microchip Technology Inc. There are four devices (PIC16F873, PIC16F874, PIC16F876 and PIC16F877) covered by this data sheet. The PIC16F876/873 devices come in 28-pin packages and the PIC16F877/874 devices come in 40- pin packages. The 28-pin devices do not have a Paral- lel Slave Port implemented. ...
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... Synchronous USART Serial Port PORTA RA0/AN0 RA1/AN1 RA2/AN2/V - REF RA3/AN3/V + REF RA4/T0CKI RA5/AN4/SS PORTB RB0/INT RB1 RB2 RB3/PGM RB4 RB5 RB6/PGC RB7/PGD PORTC RC0/T1OSO/T1CKI RC1/T1OSI/CCP2 RC2/CCP1 RC3/SCK/SCL RC4/SDI/SDA RC5/SDO RC6/TX/CK RC7/RX/DT PORTD RD7/PSP7:RD0/PSP0 PORTE RE0/AN5/RD RE1/AN6/WR RE2/AN7/CS 1999 Microchip Technology Inc. ...
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... TABLE 1-1: PIC16F873 AND PIC16F876 PINOUT DESCRIPTION DIP SOIC Pin Name Pin# Pin# OSC1/CLKIN 9 9 OSC2/CLKOUT 10 10 MCLR/V /THV RA0/AN0 2 2 RA1/AN1 3 3 RA2/AN2 REF RA3/AN3 REF RA4/T0CKI 6 6 RA5/SS/AN4 7 7 RB0/INT 21 21 RB1 22 22 RB2 23 23 RB3/PGM ...
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... RC5 can also be the SPI Data Out (SPI mode). I/O ST RC6 can also be the USART Asynchronous Transmit or Synchronous Clock. 1 I/O ST RC7 can also be the USART Asynchronous Receive or Synchronous Data. I/O = input/output P = power TTL = TTL input ST = Schmitt Trigger input 2 C modes. C mode). 1999 Microchip Technology Inc. ...
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... This buffer is a Schmitt Trigger input when configured as general purpose I/O and a TTL input when used in the Parallel Slave Port mode (for interfacing to a microprocessor bus). 4: This buffer is a Schmitt Trigger input when configured in RC oscillator mode and a CMOS input otherwise. 1999 Microchip Technology Inc. I/O/P Buffer ...
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... PIC16F87X NOTES: DS30292B-page 10 1999 Microchip Technology Inc. ...
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... RETFIE, RETLW Stack Level 1 Stack Level 2 Stack Level 8 Reset Vector Interrupt Vector Page 0 Page 1 On-Chip Program Memory Page 2 Page 3 1999 Microchip Technology Inc. FIGURE 2-2: PIC16F874/873 PROGRAM MEMORY MAP AND STACK CALL, RETURN RETFIE, RETLW On-Chip Program Memory 0000h 0004h 0005h 07FFh ...
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... Note: EEPROM Data Memory description can be found in Section 4.0 of this Data Sheet 2.2.1 GENERAL PURPOSE REGISTER FILE The register file can be accessed either directly, or indi- rectly through the File Select Register FSR. DS30292B-page 12 1999 Microchip Technology Inc. ...
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... Bank 0 Unimplemented data memory locations, read as ’0’. * Not a physical register. Note 1: These registers are not implemented on 28-pin devices. 2: These registers are reserved, maintain these registers clear. 1999 Microchip Technology Inc. (*) (*) Indirect addr. 80h TMR0 81h PCL PCL ...
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... PCLATH 18Ah 10Bh INTCON 18Bh 10Ch EECON1 18Ch 10Dh EECON2 18Dh 10Eh Reserved (2) 18Eh 10Fh (2) Reserved 18Fh 110h 190h 1A0h 120h accesses A0h - FFh 1EFh 16Fh 1F0h 170h 17Fh 1FFh Bank 3 1999 Microchip Technology Inc. ...
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... PORTD, PORTE, TRISD, and TRISE are not physically implemented on the 28-pin devices, read as ‘0’. 6: PIR2<6> and PIE2<6> are reserved on these devices; always maintain these bits clear. 1999 Microchip Technology Inc. The Special Function Registers can be classified into two sets; core (CPU) and peripheral. Those registers associated with the core functions are described in detail in this section ...
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... UA BF 0000 0000 0000 0000 — — — — — — TRMT TX9D 0000 -010 0000 -010 0000 0000 0000 0000 — — — — — — — — xxxx xxxx uuuu uuuu PCFG1 PCFG0 0--- 0000 0--- 0000 1999 Microchip Technology Inc. ...
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... These registers can be addressed from any bank. 5: PORTD, PORTE, TRISD, and TRISE are not physically implemented on the 28-pin devices, read as ‘0’. 6: PIR2<6> and PIE2<6> are reserved on these devices; always maintain these bits clear. 1999 Microchip Technology Inc. Bit 5 Bit 4 Bit 3 ...
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... Note 1: The C and DC bits operate as a borrow and digit borrow bit, respectively, in sub- traction. See the SUBLW and SUBWF instructions for examples. R-1 R/W-x R/W-x R/W bit0 R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ Value at POR reset 1999 Microchip Technology Inc. ...
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... Note: When using low voltage ICSP programming (LVP) and the pull-ups on PORTB are enabled, bit 3 in the TRISB register must be cleared to disable the pull-up on RB3 and ensure the proper operation of the device. 1999 Microchip Technology Inc. Note: To achieve a 1:1 prescaler assignment for the TMR0 register, assign the prescaler to the Watchdog Timer ...
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... GIE (INTCON<7>). User soft- ware should ensure the appropriate inter- rupt flag bits are clear prior to enabling an interrupt. R/W-0 R/W-0 R/W-0 R/W-x RBIE T0IF INTF RBIF bit0 R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ Value at POR reset 1999 Microchip Technology Inc. ...
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... TMR1IE: TMR1 Overflow Interrupt Enable bit 1 = Enables the TMR1 overflow interrupt 0 = Disables the TMR1 overflow interrupt Note 1: PSPIE is reserved on 28-pin devices; always maintain this bit clear. 1999 Microchip Technology Inc. Note: Bit PEIE (INTCON<6>) must be set to enable any peripheral interrupt. R/W-0 ...
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... GIE (INTCON<7>). User soft- ware should ensure the appropriate inter- rupt bits are clear prior to enabling an interrupt. R/W-0 R/W-0 R/W-0 R/W-0 SSPIF CCP1IF TMR2IF TMR1IF bit0 R = Readable bit W = Writable bit - n= Value at POR reset 1999 Microchip Technology Inc. ...
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... BCLIE: Bus Collision Interrupt Enable 1 = Enable Bus Collision Interrupt 0 = Disable Bus Collision Interrupt bit 2-1: Unimplemented: Read as '0' bit 0: CCP2IE: CCP2 Interrupt Enable bit 1 = Enables the CCP2 interrupt 0 = Disables the CCP2 interrupt 1999 Microchip Technology Inc. R/W-0 U-0 U-0 R/W-0 BCLIE — — CCP2IE bit0 ...
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... GIE (INTCON<7>). User soft- ware should ensure the appropriate inter- rupt flag bits are clear prior to enabling an interrupt. R/W-0 U-0 U-0 R/W-0 BCLIF — — CCP2IF bit0 2 C master mode R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ Value at POR reset 1999 Microchip Technology Inc. ...
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... BOR: Brown-out Reset Status bit Brown-out Reset occurred Brown-out Reset occurred (must be set in software after a Brown-out Reset occurs) 1999 Microchip Technology Inc. Note: BOR is unknown on POR. It must be set by the user and checked on subsequent rests to see if BOR is clear, indicating a brown- out has occurred. The BOR status bit is a don’ ...
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... BCF PCLATH,4 BSF PCLATH,3 CALL SUB1_P1 : : ORG 0x900 SUB1_P1 : : : RETURN RETLW and RETFIE instruc- CALL OF A SUBROUTINE IN PAGE 1 FROM PAGE 0 ;Select page 1 (800h-FFFh) ;Call subroutine in ;page 1 (800h-FFFh) ;page 1 (800h-FFFh) ;called subroutine ;page 1 (800h-FFFh) ;return to Call subroutine ;in page 0 (000h-7FFh) 1999 Microchip Technology Inc. ...
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... FIGURE 2-6: DIRECT/INDIRECT ADDRESSING Direct Addressing from opcode RP1:RP0 6 bank select location select 00h Data (1) Memory 7Fh Bank 0 Note 1: For register file map detail see Figure 2-3. 1999 Microchip Technology Inc. EXAMPLE 2-2: movlw movwf NEXT clrf incf btfss goto CONTINUE : 0 IRP bank select 00 ...
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... PIC16F87X NOTES: DS30292B-page 28 1999 Microchip Technology Inc. ...
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... MOVWF ADCON1 ; as digital inputs MOVLW 0xCF ; Value used to ; initialize data ; direction MOVWF TRISA ; Set RA<3:0> as inputs ; RA<5:4> as outputs ; TRISA<7:6> are always ; read as ’0’. 1999 Microchip Technology Inc. FIGURE 3-1: BLOCK DIAGRAM OF RA3:RA0 AND RA5 PINS Data Bus Port Manual Data Latch ...
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... Input/output or slave select input for synchronous serial port or analog input Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 RA5 RA4 RA3 RA2 RA1 — — PCFG3 PCFG2 PCFG1 PCFG0 Value on: Value on all Bit 0 POR, other BOR resets RA0 --0x 0000 --0u 0000 --11 1111 --11 1111 --0- 0000 --0- 0000 1999 Microchip Technology Inc. ...
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... When using Low Voltage ICSP Programming (LVP) and the pull-ups on PORTB are enabled, bit 3 in the TRISB register must be cleared to disable the pull-up on RB3 and ensure the proper operation of the device. 1999 Microchip Technology Inc. This interrupt can wake the device from SLEEP. The ...
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... Bit 3 Bit 2 RB6 RB5 RB4 RB3 RB2 INTEDG T0CS T0SE PSA PS2 Value on: Value on all Bit 1 Bit 0 POR, other BOR resets RB1 RB0 xxxx xxxx uuuu uuuu 1111 1111 1111 1111 PS1 PS0 1111 1111 1111 1111 1999 Microchip Technology Inc. ...
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... PORT Peripheral Input Note 1: I/O pins have diode protection Port/Peripheral select signal selects between port data and peripheral output. 3: Peripheral OE (output enable) is only activated if peripheral select is active. 1999 Microchip Technology Inc. FIGURE 3-6: PORT/PERIPHERAL Select Peripheral Data Out Data Bus D WR PORT ...
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... Input/output port pin or USART Asynchronous Receive or Synchro- nous Data Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 RC5 RC4 RC3 RC2 RC1 mode). Value on Value on: all Bit 0 POR, other BOR resets RC0 xxxx xxxx uuuu uuuu 1111 1111 1111 1111 1999 Microchip Technology Inc. ...
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... PORTD and TRISD Registers This section is not applicable to the PIC16F873 or PIC16F876. PORTD is an 8-bit port with Schmitt Trigger input buff- ers. Each pin is individually configurable as an input or output. PORTD can be configured as an 8-bit wide micropro- cessor port (parallel slave port) by setting control bit PSPMODE (TRISE< ...
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... PIC16F87X 3.5 PORTE and TRISE Register This section is not applicable to the PIC16F873 or PIC16F876. PORTE has three pins, RE0/RD/AN5, RE1/WR/AN6 and RE2/CS/AN7, which are individually configurable as inputs or outputs. These pins have Schmitt Trigger input buffers. I/O PORTE becomes control inputs for the micropro- cessor port when bit PSPMODE (TRISE< ...
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... IBOV 9Fh ADCON1 ADFM — — Legend unknown unchanged unimplemented read as '0'. Shaded cells are not used by PORTE. 1999 Microchip Technology Inc. Function (1) Input/output port pin or read control input in parallel slave port mode or analog input Not a read operation 0 = Read operation. Reads PORTD register (if chip selected) ...
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... PIC16F87X 3.6 Parallel Slave Port The Parallel Slave Port is not implemented on the PIC16F873 or PIC16F876. PORTD operates as an 8-bit wide Parallel Slave Port or microprocessor port when control bit PSPMODE (TRISE<4>) is set. In slave mode asynchronously readable and writable by the external world through RD control input pin RE0/RD and WR control input pin RE1/WR ...
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... PIR1 PSPIF ADIF RCIF 8Ch PIE1 PSPIE ADIE RCIE 9Fh ADCON1 ADFM — — Legend unknown unchanged unimplemented read as '0'. Shaded cells are not used by the Parallel Slave Port. 1999 Microchip Technology Inc Bit 4 Bit 3 ...
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... PIC16F87X NOTES: DS30292B-page 40 1999 Microchip Technology Inc. ...
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... EEPROM with an address range from 0h to 3FFFh. The unused upper bits in both the EEDATH and EEDATA registers all read as “0’s”. 1999 Microchip Technology Inc. PIC16F87X The value written to program memory does not need valid instruction. Therefore 14-bit numbers can be stored in memory for use as calibration param- eters, serial numbers, packed 7-bit ASCII, etc ...
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... RD: Read Control bit 1 = Initiates an EEPROM read RD is cleared in hardware. The RD bit can only be set (not cleared) in software Does not initiate an EEPROM read DS30292B-page 42 R/W-x R/W-0 R/S-0 R/S-0 WRERR WREN WR RD bit0 R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ Value at POR reset 1999 Microchip Technology Inc. ...
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... EEPROM. The WREN bit is not cleared by hardware After a write sequence has been initiated, clearing the WREN bit will not affect the current write cycle. The WR bit will be inhibited from being set unless the WREN bit 1999 Microchip Technology Inc. EXAMPLE 4-1: DATA EEPROM READ BSF STATUS, RP1 ...
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... Bank MSByte of Program Address to read ; ; LSByte of Program Address to read ; Bank 3 ; Point to PROGRAM memory ; EEPROM Read ; memory is read in the next two cycles after BSF EECON1, Bank LSByte of Program EEDATA ; W = MSByte of Program EEDATA 1999 Microchip Technology Inc. ...
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... Generally a write failure will be a bit which was written as a '1', but reads back as a '0' (due to leakage off the bit). 1999 Microchip Technology Inc. trol bit (EECON1<7>), and then set control bit WR (EECON1<1>). The sequence in Example 4-4 must be followed to initiate a write to program memory. ...
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... Yes Yes Yes Value on: Value on Bit 0 POR, all other BOR resets RBIF 0000 000x 0000 000u xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu RD x--- x000 x--- u000 CCP2IE -r-0 0--0 -r-0 0--0 CCP2IF -r-0 0--0 -r-0 0--0 1999 Microchip Technology Inc. ...
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... Watchdog Timer PSA WDT Enable bit Note: T0CS, T0SE, PSA, PS2:PS0 are (OPTION_REG<5:0>). 1999 Microchip Technology Inc. Counter mode is selected by setting bit T0CS (OPTION_REG<5>). In counter mode, Timer0 will increment either on every rising or falling edge of pin RA4/T0CKI. The incrementing edge is determined by the Timer0 (OPTION_REG< ...
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... Writing to TMR0, when the prescaler is assigned to Timer0, will clear the prescaler count, but will not change the prescaler assignment. R/W-1 R/W-1 R/W-1 R/W-1 PSA PS2 PS1 PS0 bit Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ Value at POR reset 1999 Microchip Technology Inc. ...
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... TMR0 Timer0 module’s register 0Bh,8Bh, INTCON GIE PEIE 10Bh,18Bh 81h,181h OPTION_REG RBPU INTEDG Legend unknown unchanged unimplemented locations read as '0'. Shaded cells are not used by Timer0. 1999 Microchip Technology Inc. Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 T0IE INTE RBIE T0IF INTF ...
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... PIC16F87X NOTES: DS30292B-page 50 1999 Microchip Technology Inc. ...
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... OSC bit 0: TMR1ON: Timer1 On bit 1 = Enables Timer1 0 = Stops Timer1 1999 Microchip Technology Inc. In timer mode, Timer1 increments every instruction cycle. In counter mode, it increments on every rising edge of the external clock input. Timer1 can be enabled/disabled by setting/clearing control bit TMR1ON (T1CON<0>). Timer1 also has an internal “reset input”. This reset can be generated by either of the two CCP modules (Section 8 ...
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... The pres- caler however will continue to increment. 0 TMR1L 1 TMR1ON T1SYNC on/off (2) 1 Prescaler T1OSCEN F /4 OSC Enable Internal 0 (1) Oscillator Clock 2 T1CKPS1:T1CKPS0 TMR1CS Synchronized clock input Synchronize det Q Clock 1999 Microchip Technology Inc. ...
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... Table 6-1 shows the capacitor selection for the Timer1 oscillator. The Timer1 oscillator is identical to the LP oscillator. The user must provide a software time delay to ensure proper oscillator start-up. 1999 Microchip Technology Inc. PIC16F87X TABLE 6-1: CAPACITOR SELECTION FOR THE TIMER1 OSCILLATOR ...
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... TXIE SSPIE CCP1IE TMR2IE Value on: Value on Bit 1 Bit 0 POR, all other BOR resets INTF RBIF 0000 000x 0000 000u TMR1IF 0000 0000 0000 0000 TMR1IE 0000 0000 0000 0000 xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu 1999 Microchip Technology Inc. ...
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... Timer2 is off bit 1-0: T2CKPS1:T2CKPS0: Timer2 Clock Prescale Select bits 00 = Prescaler Prescaler Prescaler is 16 1999 Microchip Technology Inc. 7.1 Timer2 Prescaler and Postscaler The prescaler and postscaler counters are cleared when any of the following occurs: • a write to the TMR2 register • a write to the T2CON register • ...
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... TMR2IF RCIE TXIE SSPIE CCP1IE TMR2IE Value on: Value on Bit 0 POR, all other BOR resets 0000 000x 0000 000u RBIF 0000 0000 0000 0000 TMR1IF 0000 0000 0000 0000 TMR1IE 0000 0000 0000 0000 1111 1111 1111 1111 1999 Microchip Technology Inc. ...
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... PWM Capture None. PWM Compare None. 1999 Microchip Technology Inc. CCP2 Module: Capture/Compare/PWM Register1 (CCPR2) is com- prised of two 8-bit registers: CCPR2L (low byte) and CCPR2H (high byte). The CCP2CON register controls the operation of CCP2. The special event trigger is gen- erated by a compare match and will reset Timer1 and start an A/D conversion (if the A/D module is enabled) ...
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... Compare mode, trigger special event (CCPxIF bit is set, CCPx pin is unaffected); CCP1 resets TMR1; CCP2 resets TMR1 and starts an A/D conversion (if A/D module is enabled) 11xx = PWM mode DS30292A-page 58 R/W-0 R/W-0 R/W-0 R/W-0 CCPxM3 CCPxM2 CCPxM1 CCPxM0 R = Readable bit W = Writable bit bit0 U = Unimplemented bit, read as ‘0’ Value at POR reset 1999 Microchip Technology Inc. ...
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... Pin Capture and Enable edge detect TMR1H CCP1CON<3:0> Q’s 1999 Microchip Technology Inc. 8.1.2 TIMER1 MODE SELECTION Timer1 must be running in timer mode or synchronized counter mode for the CCP module to use the capture feature. In asynchronous counter mode, the capture operation may not work. 8.1.3 ...
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... TMR2 Comparator PR2 Note 1: 8-bit timer is concatenated with 2-bit internal Q clock or 2 bits of the prescaler to create 10-bit time-base. from the Section 8.3.3. SIMPLIFIED PWM BLOCK DIAGRAM CCP1CON<5:4> RC2/CCP1 (Note 1) S TRISC<2> Clear Timer, CCP1 pin and latch D.C. 1999 Microchip Technology Inc. ...
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... CCPR1H until after a match between PR2 and TMR2 occurs (i.e., the period is complete). In PWM mode, CCPR1H is a read-only register. 1999 Microchip Technology Inc. The CCPR1H register and a 2-bit internal latch are used to double buffer the PWM duty cycle. This double buffering is essential for glitchless PWM operation. ...
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... CCP2IF ---- ---0 ---- ---0 TMR1IE 0000 0000 0000 0000 — CCP2IE ---- ---0 ---- ---0 1111 1111 1111 1111 0000 0000 0000 0000 1111 1111 1111 1111 xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu 1999 Microchip Technology Inc. ...
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... Serial Peripheral Interface (SPI) 2 • Inter-Integrated Circuit (I C) Figure 9-1 shows a block diagram for the SPI mode, while Figure 9-5 and Figure 9-9 show the block dia- 2 grams for the two different I C modes of operation. 1999 Microchip Technology Inc. PIC16F87X DS30292A-page 63 ...
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... Data Transmit complete (does not include the ACK and stop bits), SSPBUF is empty DS30292A-page 64 R-0 R-0 R-0 R bit0 9-4, Figure 9-5 and Figure 9- mode only) C mode only Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ Value at POR reset 1999 Microchip Technology Inc. ...
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... I C firmware controlled master mode, 7-bit address with start and stop bit interrupts enabled 2 1111 = I C firmware controlled master mode, 10-bit address with start and stop bit interrupts enabled. 1001, 1010, 1100, 1101 = reserved 1999 Microchip Technology Inc. R/W-0 R/W-0 R/W-0 R/W-0 SSPM3 SSPM2 ...
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... C master mode only master mode only master mode only master mode only module is not in the idle mode, this bit may not R = Readable bit W = Writable bit U = Unimplemented bit, Read as ‘0’ =Value at POR reset 1999 Microchip Technology Inc. ...
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... SCK) • Clock Rate (Master mode only) • Slave Select Mode (Slave mode only) Figure 9-4 shows the block diagram of the MSSP mod- ule when in SPI mode. 1999 Microchip Technology Inc. PIC16F87X FIGURE 9-1: MSSP BLOCK DIAGRAM (SPI MODE) Read ...
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... SCK. The change of the input sample is shown based on the state of the SMP bit. The time when the SSPBUF is loaded with the received data is shown. bit6 bit5 bit3 bit4 and Figure 9-9 where the MSb bit2 bit1 bit0 bit0 bit0 1999 Microchip Technology Inc. ...
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... SDO bit7 bit6 SDI (SMP = 0) bit7 SSPIF 1999 Microchip Technology Inc. While in sleep mode, the slave can transmit/receive data. When a byte is received, the device will wake-up from sleep. Note: When the SPI module is in Slave Mode with SS pin control enabled, (SSP- CON< ...
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... SSPM3 SSPM2 SSPM1 D R/W UA POR, MCLR, Bit 0 BOR WDT RBIF 0000 000x 0000 000u TMR1IF 0000 0000 0000 0000 TMR1IE 0000 0000 0000 0000 xxxx xxxx uuuu uuuu SSPM0 0000 0000 0000 0000 BF 0000 0000 0000 0000 1999 Microchip Technology Inc. ...
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... SSPADD reg Start and Stop bit detect 1999 Microchip Technology Inc. Two pins are used for data transfer. These are the SCL pin, which is the clock, and the SDA pin, which is the data. The SDA and SCL pins are automatically config- ...
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... Read the SSPBUF register (clears bit BF) and clear flag bit SSPIF. Note: Following the Repeated Start condition (step 7) in 10-bit mode, the user only needs to match the first 7-bit address. The user does not update the SSPADD for the second half of the address. 1999 Microchip Technology Inc. ...
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... SCL S SSPIF BF (SSPSTAT<0>) SSPOV (SSPCON<6>) 1999 Microchip Technology Inc. An SSP interrupt is generated for each data transfer byte. Flag bit SSPIF (PIR1<3>) must be cleared in soft- ware. The SSPSTAT register is used to determine the status of the received byte. Note: The SSPBUF will be loaded if the SSPOV bit is set and the BF flag is cleared ...
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... Cleared in software SSPBUF is read R Transmitting Data Not ACK From SSP interrupt service routine 9-8). Receiving data ACK ’0’ ’1’ 1999 Microchip Technology Inc. ...
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... Legend unknown unchanged unimplemented read as ’0’. Shaded cells are not used by the SSP in I Note 1: These bits are reserved on the 28-pin devices; always maintain these bits clear. 2: These bits are reserved on these devices; always maintain these bits clear. 1999 Microchip Technology Inc. 9.2.4 EFFECTS OF A RESET A reset disables the SSP module and terminates the current transfer ...
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... Start bit, Stop bit, Acknowledge Generate Start bit detect, Stop bit detect Set/Reset WCOL (SSPSTAT) Write collision detect Clock Arbitration Set SSPIF, BCLIF State counter for Reset ACKSTAT, PEN (SSPCON2) end of XMIT/RCV SSPM3:SSPM0, SSPADD<6:0> Baud Rate Generator 1999 Microchip Technology Inc. ...
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... SSPBUF register to initiate transmission before the START condition is complete. In this case, the SSPBUF will not be written to and the WCOL bit will be set, indicating that a write to the SSPBUF did not occur. 1999 Microchip Technology Inc. PIC16F87X 2 9.2.7 MASTER MODE OPERATION The master device generates all of the serial clock pulses and the START and STOP conditions ...
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... SCL allowed to transition high BRG decrements (on Q2 and Q4 cycles) 02h 01h 00h (hold off) SCL is sampled high, reload takes place, and BRG starts its count. BLOCK DIAGRAM SSPADD<6:0> Reload Reload Control F /4 OSC BRG Down Counter 03h 02h 1999 Microchip Technology Inc. ...
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... FIGURE 9-12: FIRST START BIT TIMING Write to SEN bit occurs here. SDA SCL 1999 Microchip Technology Inc. Note the beginning of START condition the SDA and SCL pins are already sampled low during the START condition the SCL line is sampled low before the SDA ...
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... SSPCON2 is disabled until the Repeated Start condition is complete. Set S (SSPSTAT<3>) SDA = 1, At completion of start bit, SCL = 1 hardware clear RSEN bit and set SSPIF BRG BRG BRG Write to SSPBUF occurs here. T BRG Sr = Repeated Start 1st Bit T BRG 1999 Microchip Technology Inc. ...
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... SSPSR is still shifting out a data byte), then WCOL is set and the contents of the buffer are unchanged (the write doesn’t occur). WCOL must be cleared in software. 1999 Microchip Technology Inc. PIC16F87X 9.2.11.3 ACKSTAT STATUS FLAG In transmit mode, the ACKSTAT bit (SSPCON2<6>) is ...
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... PIC16F87X 2 FIGURE 9-14 MASTER MODE TIMING (TRANSMISSION 10-BIT ADDRESS) DS30292A-page 82 1999 Microchip Technology Inc. ...
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... WCOL STATUS FLAG If the user writes the SSPBUF when a receive is already in progress (i.e. SSPSR is still shifting in a data byte), then WCOL is set and the contents of the buffer are unchanged (the write doesn’t occur). 1999 Microchip Technology Inc. PIC16F87X DS30292A-page 83 ...
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... PIC16F87X 2 FIGURE 9-15 MASTER MODE TIMING (RECEPTION 7-BIT ADDRESS) DS30292A-page 84 1999 Microchip Technology Inc. ...
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... Set SSPIF at the end of receive Note one baud rate generator period. BRG 1999 Microchip Technology Inc. the baud rate generator counts for T is then pulled low. Following this, the ACKEN bit is auto- matically cleared, the baud rate generator is turned off, bit, ACKEN and the SSP module then goes into IDLE mode ...
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... SCL = 1 for T , followed by SDA = 1 for T BRG after SDA sampled high. P bit (SSPSTAT<4>) is set PEN bit (SSPCON2<2>) is cleared by hardware and the SSPIF bit is set T BRG BRG BRG BRG SCL brought high after T BRG BRG 1999 Microchip Technology Inc. ...
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... Release SCL, Slave device holds SCL low. SCL SDA T BRG 1999 Microchip Technology Inc. 9.2.16 SLEEP OPERATION While in sleep mode, the I addresses or data, and when an address match or complete byte transfer occurs, wake the processor from sleep (if the SSP interrupt is enabled). ...
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... S and P bits are cleared. Sample SDA. While SCL is high, SDA line pulled low by another source data doesn’t match what is driven by the master. Bus collision has occurred. SDA released by master Set bus collision interrupt bus 1999 Microchip Technology Inc. ...
Page 89
... S bit and SSPIF set because BCLIF SDA = 0, SCL = 1 S SSPIF 1999 Microchip Technology Inc. while SDA is high, a bus collision occurs, because it is assumed that another master is attempting to drive a data ’1’ during the START condition. If the SDA pin is sampled low during this count, the ...
Page 90
... Bus collision occurs, Set BCLIF. SDA = 0, SCL = 1 Set S Set SSPIF BRG T BRG s SCL pulled low after BRG Timeout Set SEN, enable start sequence if SDA = 1, SCL = 1 SDA = 0, SCL = 1 Set SSPIF Interrupts cleared in software. ’0’ ’0’ Interrupts cleared in software. 1999 Microchip Technology Inc. ...
Page 91
... RSEN ’0’ S ’0’ SSPIF 1999 Microchip Technology Inc. PIC16F87X sampled high, the BRG is reloaded and begins count- ing. If SDA goes from high to low before the BRG times out, no bus collision occurs, because no two masters can assert SDA at exactly the same time. ...
Page 92
... This is a case of another master attempting to drive a data ’0’ (Figure T BRG BRG T T BRG SCL goes low before SDA goes high Set BCLIF 9-25). SDA sampled T BRG low after T , BRG Set BCLIF ’0’ ’0’ BRG 1999 Microchip Technology Inc. ...
Page 93
... For OL FIGURE 9-27: SAMPLE DEVICE CONFIGURATION FOR I Rp SDA SCL 2 Note devices with input levels related to V line to which the pull-up resistor is also connected. 1999 Microchip Technology Inc example, with a supply voltage max = function The desired noise margin of 0 ...
Page 94
... PIC16F87X NOTES: DS30292A-page 94 1999 Microchip Technology Inc. ...
Page 95
... TRMT: Transmit Shift Register Status bit 1 = TSR empty 0 = TSR full bit 0: TX9D: 9th bit of transmit data. Can be parity bit. 1999 Microchip Technology Inc. The USART can be configured in the following modes: • Asynchronous (full duplex) • Synchronous - Master (half duplex) • Synchronous - Slave (half duplex) Bit SPEN (RCSTA< ...
Page 96
... Overrun error (Can be cleared by clearing bit CREN overrun error bit 0: RX9D: 9th bit of received data (Can be parity bit) DS30292B-page 96 R/W-0 R-0 R-0 R-x ADDEN FERR OERR RX9D bit0 R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ Value at POR reset 1999 Microchip Technology Inc. ...
Page 97
... SPEN RX9 99h SPBRG Baud Rate Generator Register Legend unknown unimplemented read as '0'. Shaded cells are not used by the BRG. 1999 Microchip Technology Inc. It may be advantageous to use the high baud rate (BRGH = 1) even for slower baud clocks. This is because the F OSC baud rate error in some cases ...
Page 98
... F = 3.6864 MHz OSC SPBRG % value ERROR (decimal 0.25 185 0.25 92 1.32 22 2.90 11 2.90 7 4. 255 - 0 SPBRG value (decimal) - 129 255 0 SPBRG value (decimal 255 255 0 1999 Microchip Technology Inc. ...
Page 99
... TXEN Baud Rate CLK SPBRG Baud Rate Generator 1999 Microchip Technology Inc. ( PIE1<4>). Flag bit TXIF will be set, regardless of the state of enable bit TXIE and cannot be cleared in soft- ware. It will reset only when new data is loaded into the TXREG register. While flag bit TXIF indicates the status of the TXREG register, another bit TRMT (TXSTA< ...
Page 100
... Transmit Shift Reg. Value on: Value on Bit 0 POR, all other BOR Resets TMR1IF 0000 0000 0000 0000 RX9D 0000 -00x 0000 -00x 0000 0000 0000 0000 TMR1IE 0000 0000 0000 0000 TX9D 0000 -010 0000 -010 0000 0000 0000 0000 1999 Microchip Technology Inc. ...
Page 101
... This timing diagram shows three words appearing on the RX input. The RCREG (receive buffer) is read after the third word, causing the OERR (overrun) bit to be set. 1999 Microchip Technology Inc. for two bytes of data to be received and transferred to the RCREG FIFO and a third byte to begin shifting to the RSR register ...
Page 102
... BRGH TRMT Value on: Value on Bit 0 POR, all other BOR Resets TMR1IF 0000 0000 0000 0000 RX9D 0000 -00x 0000 -00x 0000 0000 0000 0000 0000 0000 0000 0000 TX9D 0000 -010 0000 -010 0000 0000 0000 0000 1999 Microchip Technology Inc. ...
Page 103
... RX9 ADDEN RX9 ADDEN RSR<8> 1999 Microchip Technology Inc. • Flag bit RCIF will be set when reception is com- plete, and an interrupt will be generated if enable bit RCIE was set. • Read the RCSTA register to get the ninth bit and determine if any error occurred during reception. ...
Page 104
... WORD 1 RCREG Stop bit WORD 1 RCREG Value on: Value on Bit 0 POR, all other BOR Resets 0000 0000 RX9D 0000 000x 0000 000x 0000 0000 0000 0000 0000 0000 TX9D 0000 -010 0000 -010 0000 0000 0000 0000 1999 Microchip Technology Inc. ...
Page 105
... The DT and CK pins will revert to hi-imped- ance. If either bit CREN or bit SREN is set during a transmission, the transmission is aborted and the DT 1999 Microchip Technology Inc. PIC16F87X pin reverts to a hi-impedance state (for a reception). The CK pin will remain an output if bit CSRC is set (internal clock) ...
Page 106
... Resets BOR TMR1IF 0000 0000 0000 0000 RX9D 0000 -00x 0000 -00x 0000 0000 0000 0000 TMR1IE 0000 0000 0000 0000 TX9D 0000 -010 0000 -010 0000 0000 0000 0000 bit 1 bit 7 WORD 2 ’1’ bit6 bit7 1999 Microchip Technology Inc. ...
Page 107
... Read RXREG Note: Timing diagram demonstrates SYNC master mode with bit SREN = '1' and bit BRG = '0'. 1999 Microchip Technology Inc. OERR set. The ninth receive bit is buffered the same way as the receive data. Reading the RCREG register will load bit RX9D with a new value, therefore it ...
Page 108
... RCIE was set. 6. Read the RCSTA register to get the ninth bit (if enabled) and determine if any error occurred during reception. 7. Read the 8-bit received data by reading the RCREG register any error occurred, clear the error by clearing bit CREN. 1999 Microchip Technology Inc. ...
Page 109
... SPBRG Baud Rate Generator Register Legend unknown unimplemented read as '0'. Shaded cells are not used for Synchronous Slave Reception. Note 1: Bits PSPIE and PSPIF are reserved on the 28-pin devices, always maintain these bits clear. 1999 Microchip Technology Inc. Bit 5 Bit 4 Bit 3 ...
Page 110
... PIC16F87X NOTES: DS30292B-page 110 1999 Microchip Technology Inc. ...
Page 111
... ADON: A/D On bit 1 = A/D converter module is operating 0 = A/D converter module is shutoff and consumes no operating current Note 1: These channels are not available on the 28-pin devices. 1999 Microchip Technology Inc. The A/D module has four registers. These registers are: • A/D Result High Register (ADRESH) • A/D Result Low Register (ADRESL) • ...
Page 112
... Value at POR reset C / HAN REF REF (2) Refs RA3 RA3 RA3 RA3 RA2 6 6 RA3 V 5/1 SS RA3 RA2 4/2 RA3 RA2 3/2 RA3 RA2 2 1 RA3 RA2 1/2 1999 Microchip Technology Inc. ...
Page 113
... Read A/D Result register (ADRESH:ADRESL), clear bit ADIF if required. 7. For next conversion step 1 or step 2 as required. The A/D conversion time per bit is defined minimum wait required before next acquisition starts. 1999 Microchip Technology Inc. pair is AD PIC16F87X DS30292B-page 113 ...
Page 114
... To calculate the minimum acquisition time, T the PICmicro™ (DS33023). . The sampling 111 (1) RE2/AN7 110 (1) RE1/AN6 101 (1) RE0/AN5 100 RA5/AN4 011 RA3/AN3/V + REF 010 RA2/AN2/V - REF 001 RA1/AN1 000 RA0/AN0 the minimum acquisition time, , see ACQ Mid-Range Reference Manual 1999 Microchip Technology Inc. ...
Page 115
... R = interconnect resistance sampling switch C = sample/hold capacitance (from DAC) HOLD 1999 Microchip Technology Inc. ) has no effect on the equation, since it cancels itself out not discharged after each conversion. HOLD delay must complete before acquisition can begin again Sampling Switch ...
Page 116
... AD Table 11-1shows the resultant T the device operating frequencies and the A/D clock AD source selected ADCS1:ADCS0 time but can vary between 2-6 s. time AD times derived from AD Maximum Device Frequency Max. 1.25 MHz 5 MHz 20 MHz Note 1 1999 Microchip Technology Inc. ...
Page 117
... Conversion Starts Holding capacitor is disconnected from analog input (typically 100 ns) Set GO bit 1999 Microchip Technology Inc. required before the next acquisition is started. After this 2T wait, acquisition on the selected channel is AD automatically started. In Figure 11-3, after the GO bit is set, the first time seg- ...
Page 118
... The value that is in the ADRESH:ADRESL registers is not modified for ADRESH:ADRESL registers will contain unknown data after a Power-on Reset. 10-Bit Result ADFM = ADRESH 10-bit Result Left Justified a Power-on Reset. The 0 0000 00 ADRESL 1999 Microchip Technology Inc. ...
Page 119
... IBOV 89h (1) PORTE — — 09h Legend unknown unchanged unimplemented read as '0'. Shaded cells are not used for A/D conversion. Note 1: These registers/bits are not available on the 28-pin devices. 1999 Microchip Technology Inc. Bit 4 Bit 3 Bit 2 Bit 1 INTE RBIE T0IF INTF TXIF ...
Page 120
... PIC16F87X NOTES: DS30292B-page 120 1999 Microchip Technology Inc. ...
Page 121
... Additional information on special features is available in the PICmicro™ Mid-Range Reference (DS33023). 1999 Microchip Technology Inc. 12.1 Configuration Bits The configuration bits can be programmed (read as '0') or left unprogrammed (read as '1') to select various device configurations. These bits are mapped in pro- gram memory location 2007h. ...
Page 122
... Power-up Timer is enabled anytime Brown-out Reset is enabled. 2: All of the CP1:CP0 pairs have to be given the same value to enable the code protection scheme listed. DS30292B-page 122 LVP BODEN CP1 CP0 PWRTE WDTE F0SC1 F0SC0 (2) (1) (1) Register: CONFIG Address 2007h bit0 1999 Microchip Technology Inc. ...
Page 123
... RF varies with the crystal chosen. FIGURE 12-2: EXTERNAL CLOCK INPUT OPERATION (HS OSC CONFIGURATION) OSC1 Clock from ext. system PIC16F87X OSC2 Open 1999 Microchip Technology Inc. TABLE 12-1: Mode XT 455 kHz 2.0 MHz 4.0 MHz HS 8.0 MHz 16.0 MHz These values are for design guidance only. See notes at bottom of page ...
Page 124
... FIGURE 12-3: RC OSCILLATOR MODE V DD ± 20 PPM Rext ± 20 PPM ± 50 PPM Cext ± 50 PPM V SS ± 30 PPM ± 30 PPM F OSC Recommended values: ) values, and the operat- EXT Internal OSC1 Clock PIC16F87X OSC2/CLKOUT / Rext 100 k Cext > 20pF 1999 Microchip Technology Inc. ...
Page 125
... On-chip 10-bit Ripple counter RC OSC Note 1: This is a separate oscillator from the RC oscillator of the CLKIN pin. 1999 Microchip Technology Inc. PIC16F87X WDT Reset, on MCLR reset during SLEEP, and Brown- out Reset (BOR). They are not affected by a WDT Wake-up, which is viewed as the resumption of normal operation ...
Page 126
... BODEN in the Configuration Word). Bit1 is POR (Power-on Reset Status bit cleared on a Power-on Reset and unaffected otherwise. The user must set this bit following a Power-on Reset. BOR BOR for BOR . The BOR should DD with BOR 1999 Microchip Technology Inc. ...
Page 127
... Brown-out Reset Interrupt wake-up from SLEEP Legend unchanged unknown unimplemented bit read as '0'. Note 1: When the wake-up is due to an interrupt and the GIE bit is set, the PC is loaded with the interrupt vector (0004h). 1999 Microchip Technology Inc. Power-up Brown-out PWRTE = 1 1024T ...
Page 128
... Microchip Technology Inc. ...
Page 129
... See Table 12-5 for reset value for specific condition. FIGURE 12-5: TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED MCLR INTERNAL POR PWRT TIME-OUT OST TIME-OUT INTERNAL RESET 1999 Microchip Technology Inc. Power-on Reset, MCLR Resets Brown-out Reset WDT Reset 877 ---- --qq ---- --uu 877 1111 1111 ...
Page 130
... PWRT TIME-OUT OST TIME-OUT INTERNAL RESET FIGURE 12-8: SLOW RISE TIME (MCLR TIED MCLR INTERNAL POR PWRT TIME-OUT OST TIME-OUT INTERNAL RESET DS30292B-page 130 T PWRT T PWRT ) PWRT T OST ): CASE OST ): CASE OST 1999 Microchip Technology Inc. ...
Page 131
... TMR2IE TMR1IF TMR1IE CCP2IF CCP2IE BCLIF BCLIE The following table shows which devices have which interrupts. Device T0IF INTF RBIF PSPIF ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF EEIF BCLIF CCP2IF PIC16F876/873 Yes Yes Yes - PIC16F877/874 Yes Yes Yes Yes 1999 Microchip Technology Inc. ...
Page 132
... PCLATH_TEMP and STATUS_TEMP, are only defined in bank 0. Since the upper 16 bytes of each bank are common in the PIC16F876/877 devices, temporary holding regis- ters W_TEMP, STATUS_TEMP and PCLATH_TEMP should be placed in here. These 16 locations don’t require banking and therefore, make it easier for con- text save and restore ...
Page 133
... RBPU Legend: Shaded cells are not used by the Watchdog Timer. Note 1: See Register 12-1 for operation of these bits. 1999 Microchip Technology Inc. WDT time-out period values may be found in the Elec- trical Specifications section under parameter #31. Val- ues for the WDT prescaler (actually a postscaler, but shared with the Timer0 prescaler) may be assigned using the OPTION_REG register ...
Page 134
... SLEEP instruction completes. To determine whether a SLEEP instruction executed, test the PD bit. If the PD bit is set, the SLEEP instruction was executed as a NOP. To ensure that the WDT is cleared, a CLRWDT instruc- tion should be executed before a SLEEP instruction. 2 C). 1999 Microchip Technology Inc. ...
Page 135
... Program Verification/Code Protection If the code protection bit(s) have not been pro- grammed, the on-chip program memory can be read out for verification purposes. 1999 Microchip Technology Inc OST (2) T Interrupt Latency (Note 2) ...
Page 136
... For all other cases of low volt- age ICSP, the part may be programmed at the normal operating voltage. This means calibration values, unique user IDs or user code can be reprogrammed or added. 1999 Microchip Technology Inc but can IHH to the MCLR on ...
Page 137
... NOP. One instruc- tion cycle consists of four oscillator periods. Thus, for an oscillator frequency of 4 MHz, the normal instruction 1999 Microchip Technology Inc. PIC16F87X execution time conditional test is true or the program counter is changed as a result of an instruc- tion, the instruction execution time ...
Page 138
... TO,PD 0000 0110 0100 1kkk kkkk kkkk Z 1000 kkkk kkkk 00xx kkkk kkkk 0000 0000 1001 01xx kkkk kkkk 0000 0000 1000 TO,PD 0000 0110 0011 C,DC,Z 110x kkkk kkkk Z 1010 kkkk kkkk Mid-Range MCU Family ™ 1999 Microchip Technology Inc. ...
Page 139
... Operation: (W) .AND. (k) (W) Status Affected: Z Description: The contents of W register are AND’ed with the eight bit literal 'k'. The result is placed in the W register. 1999 Microchip Technology Inc. PIC16F87X ANDWF AND W with f Syntax: [ label ] ANDWF f,d Operands 127 d Operation: (W) .AND. (f) ...
Page 140
... Clear Watchdog Timer [ label ] CLRWDT Syntax: Operands: None Operation: 00h 0 WDT prescaler Status Affected: TO, PD Description: CLRWDT instruction resets the Watchdog Timer. It also resets the prescaler of the WDT. Status bits TO and PD are set. f 127 (f) (W) WDT 1999 Microchip Technology Inc. ...
Page 141
... W register. If ’d’ the result is placed back in reg- ister ’f’. If the result is 1, the next instruc- tion is executed. If the result is 0, then a NOP is executed instead making instruction. CY 1999 Microchip Technology Inc. PIC16F87X GOTO Unconditional Branch Syntax: [ label ] GOTO k Operands: 0 ...
Page 142
... MOVWF Move Syntax: [ label ] MOVWF Operands 127 Operation: (W) (f) Status Affected: None Description: Move data from W register to reg- ister 'f'. NOP No Operation [ label ] Syntax: NOP Operands: None Operation: No operation Status Affected: None Description: No operation. 1999 Microchip Technology Inc. f ...
Page 143
... TOS PC Status Affected: None Description: Return from subroutine. The stack is POPed and the top of the stack (TOS) is loaded into the program counter. This is a two cycle instruction. 1999 Microchip Technology Inc. PIC16F87X RLF Rotate Left f through Carry Syntax: [ label ] RLF f,d Operands: 0 ...
Page 144
... XORWF Exclusive OR W with f [ label ] Syntax: XORWF f,d Operands 127 d [0,1] Operation: (W) .XOR. (f) destination) Status Affected: Z Description: Exclusive OR the contents of the W register with register 'f the result is stored in the W register the result is stored back in register 'f'. 1999 Microchip Technology Inc. ...
Page 145
... A full featured editor • A project manager • Customizable tool bar and key mapping • A status bar • On-line help 1999 Microchip Technology Inc. PIC16F87X MPLAB allows you to: • Edit your source files (either assembly or ‘C’) • One touch assemble (or compile) and download ...
Page 146
... PICmicro MCU. 14.7 PICMASTER/PICMASTER CE The PICMASTER system from Microchip Technology is a full-featured, professional quality emulator system. This flexible in-circuit emulator provides a high-quality, universal platform for emulating Microchip 8-bit PICmicro microcontrollers (MCUs). PICMASTER sys- tems are sold worldwide, with a CE compliant model available for European Union (EU) countries ...
Page 147
... SIMICE is an entry-level hardware development sys- tem designed to operate in a PC-based environment with Microchip’s simulator MPLAB-SIM. Both SIMICE and MPLAB-SIM run under Microchip Technology’s MPLAB Integrated Development Environment (IDE) software. Specifically, SIMICE provides hardware sim- ulation for Microchip’s PIC12C5XX, PIC12CE5XX, and PIC16C5X families of PICmicro 8-bit microcontrollers ...
Page 148
... Programming Tools K L evaluation and programming tools support EE OQ Microchips HCS Secure Data Products. The HCS eval- uation kit includes an LCD display to show changing codes, a decoder to decode transmissions, and a pro- gramming interface to program test transmitters. DS30292B-page 148 PIC17C756, 1999 Microchip Technology Inc. ...
Page 149
... PIC16C6X á á á á PIC16C5X á á á á PIC14000 á á á á PIC12CXXX Tools Software Emulators 1999 Microchip Technology Inc. á á á á á á á á á á á á á á á á á á ...
Page 150
... PIC16F87X NOTES: DS30292B-page 150 1999 Microchip Technology Inc. ...
Page 151
... This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. 1999 Microchip Technology Inc. (except V , MCLR. and RA4).......................................... -0. ...
Page 152
... V 5.5 V 5.0 V 4.5 V 4.0 V 3.5 V 3.0 V 2 (6.0 MHz/V) (V MAX Note the minimum voltage of the PICmicro DDAPPMIN Note 2: F has a maximum frequency of 10MHz. MAX DS30292B-page 152 16 MHz Frequency 4 MHz 10 MHz Frequency - 2 MHz DDAPPMIN ® 20 MHz device in the application. 1999 Microchip Technology Inc. ...
Page 153
... FIGURE 15-3: PIC16FXXX-04 VOLTAGE-FREQUENCY GRAPH 6.0 V 5.5 V 5.0 V 4.5 V 4.0 V 3.5 V 3.0 V 2.5 V 2.0 V 1999 Microchip Technology Inc. PIC16CXXX-04 4 MHz Frequency PIC16F87X DS30292B-page 153 ...
Page 154
... Rext in kOhm. measurement. BOR +85°C for industrial and Conditions = 4 MHz 5.5V (Note MHz 5. 5. 4.0V, WDT enabled 4.0V, WDT disabled + 4.0V, WDT disabled and voltage trip point is reached. 1999 Microchip Technology Inc. ...
Page 155
... This is not tested. 6: The current is the additional current consumed when this peripheral is enabled. This current should be added to the base measurement 1999 Microchip Technology Inc. Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C 0°C Min Typ† Max Units 2 ...
Page 156
... For entire V range DD For entire V range DD Note1 For entire V range DD for V = 4 PIN Pin at hi-imped- PIN DD ance V V PIN XT, HS and LP osc PIN DD configuration I = 8.5 mA 4. 1.6 mA 4.5V - +85 C 1999 Microchip Technology Inc. ...
Page 157
... The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels represent normal operating conditions. Higher leakage current may be measured at different input voltages. 3: Negative current is defined as current sourced by the pin. 1999 Microchip Technology Inc. Standard Operating Conditions (unless otherwise stated) Operating temperature -40° ...
Page 158
... specifications only) T Time osc OSC1 SCK T0CKI t1 T1CKI Period R Rise V Valid Z Hi-impedance High High Low Low SU Setup STO STOP condition Load condition Pin 1999 Microchip Technology Inc. ...
Page 159
... All devices are tested to operate at "min." values with an external clock applied to the OSC1/CLKIN pin. When an external clock input is used, the "Max." cycle time limit is "DC" (no clock) for all devices. 1999 Microchip Technology Inc ...
Page 160
... Note 1 35 100 ns Note 1 35 100 ns Note 1 — 0. Note 1 CY — — ns Note 1 — — ns Note 1 100 255 ns — — ns — — ns — — — 145 — 145 ns — — ns — — ns 1999 Microchip Technology Inc. ...
Page 161
... Brown-out Reset pulse width BOR Legend: * These parameters are characterized but not tested. † Data in "Typ" column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. 1999 Microchip Technology Inc. PIC16F87X BOR ...
Page 162
... Extended(LF) Greater of — Extended(LF) 100 — DC — 2Tosc — 7Tosc 1999 Microchip Technology Inc. 48 Units Conditions — ns Must also meet parameter 42 — ns — ns Must also meet parameter 42 — ns — ns — prescale value (2, 4, ..., 256) — ...
Page 163
... TccF CCP1 and CCP2 output fall time * These parameters are characterized but not tested. † Data in "Typ" column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. 1999 Microchip Technology Inc Min 0 ...
Page 164
... Data in "Typ" column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. DS30292B-page 164 65 62 Min Typ† Max Units 20 — 25 — 20 — Extended(LF) 35 — — — — — 10 — 63 Conditions — ns — ns Extended Range Only — ns — Extended Range Only 30 ns 1999 Microchip Technology Inc. ...
Page 165
... Note: Refer to Figure 15-4 for load conditions. FIGURE 15-13: SPI MASTER MODE TIMING (CKE = 1, SMP = SCK (CKP = SCK (CKP = 1) MSb SDO SDI MSb IN 74 Note: Refer to Figure 15-4 for load conditions. 1999 Microchip Technology Inc BIT6 - - - - - -1 MSb 75, 76 BIT6 - - - - BIT6 - - - - - -1 LSb 75, 76 BIT6 - - - -1 LSb IN ...
Page 166
... SS 70 SCK (CKP = 0) 71 SCK (CKP = 1) MSb SDO SDI SDI MSb IN 74 Note: Refer to Figure 15-4 for load conditions. DS30292B-page 166 MSb BIT6 - - - - - -1 75, 76 BIT6 - - - - BIT6 - - - - - -1 LSb 75, 76 BIT6 - - - -1 LSb LSb 77 LSb 1999 Microchip Technology Inc. ...
Page 167
... Setup time START condition HD STA Hold time STOP condition SU STO Setup time STOP condition HD STO Hold time 1999 Microchip Technology Inc. Min 100 100 Standard(F) — Extended(LF) — — 10 — Extended(LF) — — Standard(F) — ...
Page 168
... Cb is specified to be from 10 to 400 pF s Only relevant for repeated START condition s s After this period the first clock pulse is generated Note Note Time the bus must be free before a new transmission can s start pF 1999 Microchip Technology Inc. ...
Page 169
... SYNC RCV (MASTER & SLAVE) Data setup before CK 126 TckL2dtl Data hold after CK †: Data in “Typ” column unless otherwise stated. These parameters are for design guidance only and are not tested. 1999 Microchip Technology Inc. 121 122 Min Standard(F) — Extended(LF) — ...
Page 170
... AIN REF V Absolute minimum electrical spec. To ensure 10-bit accuracy Average current consumption when A/D is on. A (Note 1) A During V acquisition. AIN Based on differential of V HOLD charge C , see AIN HOLD Section 11.1. A During A/D Conversion cycle 1999 Microchip Technology Inc. ...
Page 171
... Data in "Typ" column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. § This specification ensured by design. Note 1: ADRES register may be read on the following T 2: See Section 11.1 for min conditions. 1999 Microchip Technology Inc. (1) 131 130 8 7 ...
Page 172
... PIC16F87X NOTES: DS30292B-page 172 1999 Microchip Technology Inc. ...
Page 173
... C. ’Max’ or ’min’ represents (mean + (mean - 3 ) respectively, where is standard deviation, over the whole temper- ature range. Graphs and Tables not available at this time. 1999 Microchip Technology Inc. PIC16F87X DS30292B-page 173 ...
Page 174
... PIC16F87X NOTES: DS30292B-page 174 1999 Microchip Technology Inc. ...
Page 175
... For OTP marking beyond this, certain price adders apply. Please check with your Microchip Sales Office. For QTP devices, any special marking adders are included in QTP price. 1999 Microchip Technology Inc. PIC16F87X Example PIC16F876-20/SP 9917HAT Example PIC16F876-04/SO 9910SAA DS30292B-page 175 ...
Page 176
... PDIP XXXXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXXXX AABBCDE 44-Lead TQFP XXXXXXXXXX XXXXXXXXXX XXXXXXXXXX AABBCDE 44-Lead MQFP XXXXXXXXXX XXXXXXXXXX XXXXXXXXXX AABBCDE 44-Lead PLCC XXXXXXXXXX XXXXXXXXXX XXXXXXXXXX AABBCDE DS30292B-page 176 Example PIC16F877-04/P 9912SAA Example PIC16F877 -04/PT 9911HAT Example PIC16F877 -20/PQ 9904SAT Example PIC16F877 -20/L 9903SAT 1999 Microchip Technology Inc. ...
Page 177
... Dimensions “D” and “E” do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.010” (0.254 mm) per side or 0.020” (0.508 mm) more than dimensions “D” or “E.” 1999 Microchip Technology Inc ...
Page 178
... A1 MILLIMETERS NOM MAX 1.27 28 2.36 2.50 2.64 1.22 1.47 1.73 0.10 0.19 0.28 17.78 17.93 18.08 7.42 7.51 7.59 10.01 10.33 10.64 0.25 0.50 0.74 0.13 0.13 0.25 0.13 0.13 0.25 0.28 0.41 0. 0.25 0.38 0.51 0.23 0.27 0.30 0.36 0.42 0. 1999 Microchip Technology Inc. ...
Page 179
... Dimensions “D” and “E” do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.010” (0.254 mm) per side or 0.020” (0.508 mm) more than dimensions “D” or “E.” 1999 Microchip Technology Inc ...
Page 180
... A1 MILLIMETERS* MIN NOM MAX 0. 1.00 1.10 1.20 0.38 0.64 0.89 0.05 0.10 0.15 0.08 0.08 0.25 0.08 0.14 0.20 0.13 0.25 0.38 0 3.5 7 0.08 0.20 0.33 0.09 0.15 0.20 0.30 0.38 0.45 11.75 12.00 12.25 11.75 12.00 12.25 9.90 10.00 10.10 9.90 10.00 10.10 0.64 0.89 1. 1999 Microchip Technology Inc. ...
Page 181
... Dimensions “D” and “E” do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.010” (0.254 mm) per side or 0.020” (0.508 mm) more than dimensions “D” or “E.” JEDEC equivalent:MS-022 AB 1999 Microchip Technology Inc 45° ...
Page 182
... MILLIMETERS MIN NOM MAX 44 1.27 4.19 4.38 4.57 2.41 2.60 2.79 0.38 0.57 0.76 0.61 0.74 0.86 1.02 1.14 1.27 0.00 0.13 0.25 17.40 17.53 17.65 17.40 17.53 17.65 16.51 16.59 16.66 16.51 16.59 16.66 15.49 15.75 16.00 15.49 15.75 16.00 11 0.20 0.25 0.30 0.66 0.74 0.81 0.38 0.46 0.53 1.27 1.46 1.65 0.08 0.13 0.25 0.38 0.64 0. 1999 Microchip Technology Inc. ...
Page 183
... CCP 2 Program Memory 4K, 8K EPROM RAM 192, 368 bytes EEPROM data None Other 1999 Microchip Technology Inc. Revision Description PIC16F876/873 8 channels, 10bits yes 40-pin PDIP, 44-pin TQFP, 44-pin MQFP, 44-pin PLCC PIC16C7X 28/ Slave) PSP, USART, SSP (SPI, I ...
Page 184
... PIC16F87X NOTES: DS30292B-page 184 1999 Microchip Technology Inc. ...
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... Application Note AN578, "Use of the SSP Module in the I2C Multi-Master Environment." ............................... 71 Application Notes AN552 (Implementing Wake-up on Key Strokes Using PIC16CXXX) ....................................... 31 AN556 (Table Reading Using PIC16CXX) ................. 26 Architecture PIC16F873/PIC16F876 Block Diagram ....................... 5 PIC16F874/PIC16F877 Block Diagram ....................... 6 Assembler MPASM Assembler .................................................. 145 B Banking, Data Memory ................................................ 12, 18 Baud Rate Generator ......................................................... 78 BCLIF ...
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... RBIF Bit ............................................................... 20, 31 T0IE Bit ...................................................................... 20 T0IF Bit ...................................................................... 20 2 Inter-Integrated Circuit (I C) .............................................. 63 Internal Sampling Switch (Rss) Impedence ..................... 114 Interrupt Sources ..................................................... 121, 131 Block Diagram ......................................................... 131 Interrupt on Change (RB7:RB4 ) ............................... 31 RB0/INT Pin, External ...................................... 7, 8, 132 TMR0 Overflow ........................................................ 132 USART Receive/Transmit Complete ......................... 95 1999 Microchip Technology Inc. ...
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... PIC16F87X PCLATH Register ............................................ 15, 16, 17, 26 PCON Register .................................................... 17, 25, 126 BOR Bit ...................................................................... 25 POR Bit ...................................................................... 25 PIC16F876 Pinout Description ............................................ 7 PICDEM-1 Low-Cost PICmicro Demo Board .................. 147 PICDEM-2 Low-Cost PIC16CXX Demo Board ................ 147 PICDEM-3 Low-Cost PIC16CXXX Demo Board ............. 147 PICSTART Plus Entry Level Development System ...... 147 PIE1 Register ...
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... Slave Mode ................................................................ 69 SS ...................................................................................... 67 SSP .................................................................................... 63 Block Diagram (SPI Mode) ........................................ 67 RA5/SS/AN4 Pin ...................................................... 7, 8 RC3/SCK/SCL Pin ................................................... 7, 8 RC4/SDI/SDA Pin .................................................... 7, 8 RC5/SDO Pin ........................................................... 7, 8 SPI Mode ................................................................... 67 SSPADD .................................................................... 72 SSPBUF .............................................................. 68, 72 SSPCON1 ................................................................. 65 SSPCON2 ................................................................. 66 SSPSR ................................................................ 68, 72 SSPSTAT ............................................................ 64 SSP SSP I C Operation .................................................... 71 1999 Microchip Technology Inc. ...
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... Clock Source Select (T0CS Bit) ................................. 19 Overflow Enable (T0IE Bit) ........................................ 20 Overflow Flag (T0IF Bit) ..................................... 20, 132 Overflow Interrupt .................................................... 132 RA4/T0CKI Pin, External Clock ............................... 7, 8 Timer1 ................................................................................ 51 RC0/T1OSO/T1CKI Pin ........................................... 7, 8 RC1/T1OSI/CCP2 Pin .............................................. 7, 8 1999 Microchip Technology Inc. PIC16F87X Timers Timer0 External Clock ................................................... 48 Interrupt ............................................................. 47 Prescaler ........................................................... 48 Prescaler Block Diagram ................................... 47 Section ...
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... Time-out Period ....................................................... 133 WDT Reset, Normal Operation ................ 125, 127, 128 WDT Reset, SLEEP ................................. 125, 127, 128 Waveform for General Call Address Sequence ................. 74 WCOL .................................................. 65, 79, 81, 83, 85, 86 WCOL Status Flag ............................................................. 79 Write Collision Detect bit, WCOL ....................................... 65 WWW, On-Line Support ...................................................... 4 1999 Microchip Technology Inc. ...
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... Trademarks: The Microchip name, logo, PIC, PICmicro, PICSTART, PICMASTER, PRO MATE and MPLAB are regis- tered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. Flex ROM and fuzzy LAB are trademarks and SQTP is a service mark of Microchip in the U ...
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... Is there any incorrect or misleading information (what and where)? 7. How would you improve this document? 8. How would you improve our software, systems, and silicon products? DS30292B-page 192 Total Pages Sent FAX: (______) _________ - _________ N Literature Number: DS30292B 1999 Microchip Technology Inc. ...
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... Register on our web site (www.microchip.com/cn) to receive the most current information on our products. 1999 Microchip Technology Inc. /XX XXX Examples: Package Pattern f) PIC16F877 -20/P 301 = Commercial temp., PDIP package, 4 MHz, normal V pattern #301. g) PIC16F876 - 04I/SO = Industrial temp., SOIC package, 200 kHz, Extended V (2) ;V range 4. PIC16F877 - 04I/P = Industrial temp., PDIP ( range 2.0V to 5.5V DD ...
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... Information contained in this publication regarding device applications and the like is intended for suggestion only and may be superseded by updates. No representation or warranty is given and no liability is assumed by Microchip Technology Incorporated with respect to the accuracy or use of such information, or infringement of patents or other intellectual property rights arising from such use or otherwise. Use of Microchip’s products as critical components in life support systems is not authorized except with express written approval by Microchip ...