16F876 Microchip Technology, 16F876 Datasheet - Page 76

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16F876

Manufacturer Part Number
16F876
Description
28/40-pin 8-Bit CMOS FLASH Microcontrollers
Manufacturer
Microchip Technology
Datasheet
PIC16F87X
9.2.5
Master mode of operation is supported by interrupt
generation on the detection of the START and STOP
conditions. The STOP (P) and START (S) bits are
cleared from a reset or when the MSSP module is dis-
abled. Control of the I
P bit is set, or the bus is idle with both the S and P bits
clear.
FIGURE 9-9:
DS30292A-page 76
SDA
SCL
MASTER MODE
SSP BLOCK DIAGRAM (I
2
C bus may be TACKEN when the
SDA in
Bus Collision
SCL in
Read
MSb
Write collision detect
end of XMIT/RCV
Start bit, Stop bit,
Clock Arbitration
State counter for
Start bit detect,
2
Stop bit detect
Acknowledge
C MASTER MODE)
Generate
SSPBUF
SSPSR
LSb
Write
In master mode, the SCL and SDA lines are manipu-
lated by the MSSP hardware.
The following events will cause the SSP Interrupt Flag
bit, SSPIF, to be set (SSP Interrupt if enabled):
• START condition
• STOP condition
• Data transfer byte transmitted/received
• Acknowledge transmit
• Repeated Start
Clock
Data Bus
Shift
Internal
Set/Reset, S, P, WCOL (SSPSTAT)
Set SSPIF, BCLIF
Reset ACKSTAT, PEN (SSPCON2)
1999 Microchip Technology Inc.
SSPADD<6:0>
SSPM3:SSPM0,
Baud
Rate
Generator

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