16F876 Microchip Technology, 16F876 Datasheet - Page 73

• Manufacturer Part Number: 16F876
• Description: 28/40-pin 8-Bit CMOS FLASH Microcontrollers
• Manufacturer: Microchip Technology

9.2.1.2
When the R/W bit of the address byte is clear and an
address match occurs, the R/W bit of the SSPSTAT
register is cleared. The received address is loaded into
the SSPBUF register.
When the address byte overflow condition exists, then
no acknowledge (ACK) pulse is given. An overflow con-
dition is defined as either bit BF (SSPSTAT<0>) is set
or bit SSPOV (SSPCON<6>) is set.
TABLE 9-2
9.2.1.3
When the R/W bit of the incoming address byte is set
and an address match occurs, the R/W bit of the
SSPSTAT register is set. The received address is
loaded into the SSPBUF register. The ACK pulse will
be sent on the ninth bit, and the SCL pin is held low.
The transmit data must be loaded into the SSPBUF
register, which also loads the SSPSR register. Then the
SCL pin should be enabled by setting bit CKP (SSP-
CON<4>). The master must monitor the SCL pin prior
to asserting another clock pulse. The slave devices
may be holding off the master by stretching the clock.
The eight data bits are shifted out on the falling edge of
the SCL input. This ensures that the SDA signal is valid
during the SCL high time
FIGURE 9-6:
Note 1: Shaded cells show the conditions where the user software did not properly clear the overflow condition.
SDA
SCL
SSPIF
BF (SSPSTAT<0>)
1999 Microchip Technology Inc.
SSPOV (SSPCON<6>)
Transfer is Received
Status Bits as Data
BF
0
1
1
0
S
SLAVE RECEPTION
SLAVE TRANSMISSION
A7 A6 A5 A4 A3 A2 A1
1
SSPOV
2
Receiving Address
DATA TRANSFER RECEIVED BYTE ACTIONS
I
2
0
0
1
1
3
C WAVEFORMS FOR RECEPTION (7-BIT ADDRESS)
4
(Figure
5
6
SSPSR
9-7).
7
R/W=0
8
ACK
9
Yes
Yes
No
No
D7
SSPBUF
1
D6
2
SSPBUF register is read
Cleared in software
Receiving Data
D5
3
D4
Bit SSPOV is set because the SSPBUF register is still full.
4
D3
5
D2
6
An SSP interrupt is generated for each data transfer
byte. Flag bit SSPIF (PIR1<3>) must be cleared in soft-
ware. The SSPSTAT register is used to determine the
status of the received byte.
An SSP interrupt is generated for each data transfer
byte. The SSPIF flag bit must be cleared in software
and the SSPSTAT register is used to determine the sta-
tus of the byte transfer. The SSPIF flag bit is set on the
falling edge of the ninth clock pulse.
As a slave-transmitter, the ACK pulse from the master
receiver is latched on the rising edge of the ninth SCL
input pulse. If the SDA line is high (not ACK), then the
data transfer is complete. When the not ACK is latched
by the slave, the slave logic is reset and the slave then
monitors for another occurrence of the START bit. If the
SDA line was low (ACK), the transmit data must be
loaded into the SSPBUF register, which also loads the
SSPSR register. Then the SCL pin should be enabled
by setting the CKP bit.
Generate ACK
D1
7
Note:
Pulse
D0
8
Yes
No
No
No
ACK
9
The SSPBUF will be loaded if the SSPOV
bit is set and the BF flag is cleared. If a
read of the SSPBUF was performed, but
the user did not clear the state of the
SSPOV bit before the next receive
occurred, the ACK is not sent and the SSP-
BUF is updated.
D7
1
D6
2
D5
Receiving Data
3
D4
4
ACK is not sent.
PIC16F87X
(SSP Interrupt occurs
D3
5
D2
6
Set bit SSPIF
if enabled)
D1
7
Yes
Yes
Yes
Yes
DS30292A-page 73
D0
8
ACK
Not
9
transfer
Bus Master
terminates
P