16F876 Microchip Technology, 16F876 Datasheet - Page 43

• Manufacturer Part Number: 16F876
• Description: 28/40-pin 8-Bit CMOS FLASH Microcontrollers
• Manufacturer: Microchip Technology

4.3
To read a data memory location, the user must write the
address to the EEADR register, clear the EEPGD con-
trol bit (EECON1<7>) and then set control bit RD
(EECON1<0>). The data is available in the very next
instruction cycle of the EEDATA register, therefore it
can be read by the next instruction. EEDATA will hold
this value until another read operation or until it is writ-
ten to by the user (during a write operation).
4.4
To write an EEPROM data location, the address must
first be written to the EEADR register and the data writ-
ten to the EEDATA register. Then the sequence in
Example 4-2 must be followed to initiate the write cycle.
EXAMPLE 4-2:
The write will not initiate if the above sequence is not
exactly followed (write 55h to EECON2, write AAh to
EECON2, then set WR bit) for each byte. It is strongly
recommended that interrupts be disabled during this
code segment.
Additionally, the WREN bit in EECON1 must be set to
enable writes. This mechanism prevents accidental
writes to data EEPROM due to unexpected code exe-
cution (i.e., runaway programs). The WREN bit should
be kept clear at all times, except when updating the
EEPROM. The WREN bit is not cleared by hardware
After a write sequence has been initiated, clearing the
WREN bit will not affect the current write cycle. The WR
bit will be inhibited from being set unless the WREN bit
Required
Sequence
1999 Microchip Technology Inc.
Reading the Data EEPROM Memory
Writing to the Data EEPROM Memory
DATA EEPROM WRITE
BSF
BCF
MOVLW
MOVWF
MOVLW
MOVWF
BSF
BCF
BSF
BCF
MOVLW
MOVWF
MOVLW
MOVWF
BSF
BSF
SLEEP
BCF
STATUS, RP1
STATUS, RP0
DATA_EE_ADDR
EEADR
DATA_EE_DATA
EEDATA
STATUS, RP0
EECON1, EEPGD ; Point to DATA memory
EECON1, WREN
INTCON, GIE
55h
EECON2
AAh
EECON2
EECON1, WR
INTCON, GIE
EECON1, WREN
;
; Bank 2
;
; Data Memory Address to write
;
; Data Memory Value to write
; Bank 3
; Enable writes
; Disable Interrupts
;
; Write 55h
;
; Write AAh
; Set WR bit to begin write
; Enable Interrupts
; Wait for interrupt to signal write complete
; Disable writes
EXAMPLE 4-1:
BSF
BCF
MOVLW DATA_EE_ADDR ;
MOVWF EEADR
BSF
BCF
BSF
BCF
MOVF
is set. The WREN bit must be set on a previous instruc-
tion. Both WR and WREN cannot be set with the same
instruction.
At the completion of the write cycle, the WR bit is
cleared in hardware and the EEPROM Write Complete
Interrupt Flag bit (EEIF) is set. EEIF must be cleared by
software.
STATUS, RP1
STATUS, RP0
STATUS, RP0
EECON1, EEPGD ;Point to DATA memory
EECON1, RD
STATUS, RP0
EEDATA, W
DATA EEPROM READ
;
;Bank 2
;Data Memory Address to read
;Bank 3
;EEPROM Read
;Bank 2
;W = EEDATA
PIC16F87X
DS30292B-page 43