16F876 Microchip Technology, 16F876 Datasheet - Page 87

• Manufacturer Part Number: 16F876
• Description: 28/40-pin 8-Bit CMOS FLASH Microcontrollers
• Manufacturer: Microchip Technology

9.2.15
Clock arbitration occurs when the master, during any
receive, transmit, or repeated start/stop condition,
deasserts the SCL pin (SCL allowed to float high).
When the SCL pin is allowed to float high, the baud rate
generator (BRG) is suspended from counting until the
SCL pin is actually sampled high. When the SCL pin is
sampled high, the baud rate generator is reloaded with
the contents of SSPADD<6:0> and begins counting.
This ensures that the SCL high time will always be at
least one BRG rollover count in the event that the clock
is held low by an external device
FIGURE 9-18: CLOCK ARBITRATION TIMING IN MASTER TRANSMIT MODE
BRG overflow,
Release SCL,
If SCL = 1 Load BRG with
SSPADD<6:0>, and start count
to measure high time interval
1999 Microchip Technology Inc.
SCL
SDA
CLOCK ARBITRATION
T
BRG
(Figure
BRG overflow occurs,
Release SCL, Slave device holds SCL low.
9-18).
T
BRG
SCL line sampled once every machine cycle (T
Hold off BRG until SCL is sampled high.
9.2.16
While in sleep mode, the I
addresses or data, and when an address match or
complete byte transfer occurs, wake the processor from
sleep (if the SSP interrupt is enabled).
9.2.17
A reset disables the SSP module and terminates the
current transfer.
SLEEP OPERATION
EFFECTS OF A RESET
T
BRG
SCL = 1 BRG starts counting
clock high interval.
PIC16F87X
2
C module can receive
OSC
DS30292A-page 87
4).