16F876 Microchip Technology, 16F876 Datasheet - Page 64

• Manufacturer Part Number: 16F876
• Description: 28/40-pin 8-Bit CMOS FLASH Microcontrollers
• Manufacturer: Microchip Technology

PIC16F87X
REGISTER 9-1:
DS30292A-page 64
bit7
bit 7:
bit 6:
bit 5:
bit 4:
bit 3:
bit 2:
bit 1:
bit 0:
R/W-0
SMP
R/W-0
SMP: Sample bit
SPI Master Mode
1 = Input data sampled at end of data output time
0 = Input data sampled at middle of data output time
SPI Slave Mode
SMP must be cleared when SPI is used in slave mode
In I
1= Slew rate control disabled for standard speed mode (100 kHz and 1 MHz)
0= Slew rate control enabled for high speed mode (400 kHz)
CKE: SPI Clock Edge Select
SPI Mode:
CKP = 0
1 = Transmit happens on transistion from active clock state to idle clock state
0 = Transmit happens on transistion from idle clock state to active clock state
CKP = 1
1 = Data transmitted on falling edge of SCK
0 = Data transmitted on rising edge of SCK
In I
1 = Input levels conform to SMBUS spec
0 = Input levels conform to I
D/A: Data/Address bit (I
1 = Indicates that the last byte received or transmitted was data
0 = Indicates that the last byte received or transmitted was address
P: Stop bit
(I
1 = Indicates that a stop bit has been detected last (this bit is '0' on RESET)
0 = Stop bit was not detected last
S: Start bit
(I
1 = Indicates that a start bit has been detected last (this bit is '0' on RESET)
0 = Start bit was not detected last
R/W: Read/Write bit information (I
This bit holds the R/W bit information following the last address match. This bit is only valid from the address match to
the next start bit, stop bit or not ACK bit.
In I
1 = Read
0 = Write
In I
1 = Transmit is in progress
0 = Transmit is not in progress.
Or’ing this bit with SEN, RSEN, PEN, RCEN or ACKEN will indicate if the MSSP is in IDLE mode.
UA: Update Address (10-bit I
1 = Indicates that the user needs to update the address in the SSPADD register
0 = Address does not need to be updated
BF: Buffer Full Status bit
Receive (SPI and I
1 = Receive complete, SSPBUF is full
0 = Receive not complete, SSPBUF is empty
Transmit (I
1 = Data Transmit in progress (does not include the ACK and stop bits), SSPBUF is full
0 = Data Transmit complete (does not include the ACK and stop bits), SSPBUF is empty
CKE
2
2
C mode only. This bit is cleared when the MSSP module is disabled, SSPEN is cleared)
C mode only. This bit is cleared when the MSSP module is disabled, SSPEN is cleared)
2
2
2
2
C master or slave mode:
C Master or Slave Mode:
C slave mode:
C master mode:
SSPSTAT: SYNC SERIAL PORT STATUS REGISTER (ADDRESS: 94h)
2
D/A
R-0
C mode only)
2
C modes)
R-0
P
2
C mode only)
2
C specs
2
(Figure
C mode only)
R-0
2
S
C mode only)
9-4,
Figure 9-5
R/W
R-0
and
Figure
R-0
UA
9-6)
bit0
R-0
BF
R = Readable bit
W = Writable bit
U = Unimplemented bit, read
- n = Value at POR reset
1999 Microchip Technology Inc.
as ‘0’