16F876 Microchip Technology, 16F876 Datasheet - Page 88

• Manufacturer Part Number: 16F876
• Description: 28/40-pin 8-Bit CMOS FLASH Microcontrollers
• Manufacturer: Microchip Technology

PIC16F87X
9.2.18
Multi-Master mode support is achieved by bus arbitra-
tion. When the master outputs address/data bits onto
the SDA pin, arbitration takes place when the master
outputs a ’1’ on SDA by letting SDA float high and
another master asserts a ’0’. When the SCL pin floats
high, data should be stable. If the expected data on
SDA is a ’1’ and the data sampled on the SDA pin = ’0’,
a bus collision has TACKEN place. The master will set
the Bus Collision Interrupt Flag, BCLIF and reset the
I
If a transmit was in progress when the bus collision
occurred, the transmission is halted, the BF flag is
cleared, the SDA and SCL lines are deasserted, and
the SSPBUF can be written to. When the user services
the bus collision interrupt service routine, and if the I
bus is free, the user can resume communication by
asserting a START condition.
FIGURE 9-19: BUS COLLISION TIMING FOR TRANSMIT AND ACKNOWLEDGE
DS30292A-page 88
2
C port to its IDLE state.
SDA
SCL
BCLIF
MULTI -MASTER COMMUNICATION, BUS
COLLISION, AND BUS ARBITRATION
(Figure
Data changes
while SCL = 0
9-19).
SDA released
by master
2
C
SDA line pulled low
by another source
If a START, Repeated Start, STOP or Acknowledge
condition was in progress when the bus collision
occurred, the condition is aborted, the SDA and SCL
lines are deasserted, and the respective control bits in
the SSPCON2 register are cleared. When the user
services the bus collision interrupt service routine, and
if the I
tion by asserting a START condition.
The Master will continue to monitor the SDA and SCL
pins, and if a STOP condition occurs, the SSPIF bit will
be set.
A write to the SSPBUF will start the transmission of
data at the first data bit, regardless of where the trans-
mitter left off when the bus collision occurred.
In multi-master mode, the interrupt generation on the
detection of start and stop conditions allows the deter-
mination of when the bus is free. Control of the I
can be TACKEN when the P bit is set in the SSPSTAT
register, or the bus is idle and the S and P bits are
cleared.
2
C bus is free, the user can resume communica-
Sample SDA. While SCL is high,
data doesn’t match what is driven
by the master.
Bus collision has occurred.
Set bus collision
interrupt.
1999 Microchip Technology Inc.
2
C bus