16F876 Microchip Technology, 16F876 Datasheet - Page 16

• Manufacturer Part Number: 16F876
• Description: 28/40-pin 8-Bit CMOS FLASH Microcontrollers
• Manufacturer: Microchip Technology

PIC16F87X
TABLE 2-1:
DS30292B-page 16
80h
81h
82h
83h
84h
85h
86h
87h
88h
89h
8Ah
8Bh
8Ch
8Dh
8Eh
8Fh
90h
91h
92h
93h
94h
95h
96h
97h
98h
99h
9Ah
9Bh
9Ch
9Dh
9Eh
9Fh
Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented read as ’0’, r = reserved.
Note 1: The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<12:8> whose
Addres
Bank 1
(4)
(4)
(4)
(4)
(5)
(5)
s
(1,4)
(4)
2: Other (non power-up) resets include external reset through MCLR and Watchdog Timer Reset.
3: Bits PSPIE and PSPIF are reserved on the 28-pin devices; always maintain these bits clear.
4: These registers can be addressed from any bank.
5: PORTD, PORTE, TRISD, and TRISE are not physically implemented on the 28-pin devices, read as ‘0’.
6: PIR2<6> and PIE2<6> are reserved on these devices; always maintain these bits clear.
INDF
OPTION_R
EG
PCL
STATUS
FSR
TRISA
TRISB
TRISC
TRISD
TRISE
PCLATH
INTCON
PIE1
PIE2
PCON
—
—
SSPCON2
PR2
SSPADD
SSPSTAT
—
—
—
TXSTA
SPBRG
—
—
—
—
ADRESL
ADCON1
Shaded locations are unimplemented, read as ‘0’.
contents are transferred to the upper byte of the program counter.
Name
SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)
Addressing this location uses contents of FSR to address data memory (not a physical register)
Program Counter’s (PC) Least Significant Byte
Indirect data memory address pointer
PORTB Data Direction Register
PORTC Data Direction Register
PORTD Data Direction Register
Unimplemented
Unimplemented
Timer2 Period Register
Synchronous Serial Port (I
Unimplemented
Unimplemented
Unimplemented
Baud Rate Generator Register
Unimplemented
Unimplemented
Unimplemented
Unimplemented
A/D Result Register Low Byte
PSPIE
GCEN
RBPU
CSRC
ADFM
Bit 7
SMP
IRP
GIE
IBF
—
—
—
—
(3)
ACKSTAT
INTEDG
Bit 6
PEIE
ADIE
RP1
OBF
CKE
TX9
(6)
—
—
—
—
PORTA Data Direction Register
2
ACKDT
T0CS
C mode) Address Register
TXEN
Bit 5
RCIE
IBOV
T0IE
RP0
D/A
—
—
—
—
Write Buffer for the upper 5 bits of the Program Counter
PSPMODE
ACKEN
SYNC
Bit 4
T0SE
INTE
EEIE
TXIE
TO
—
—
P
PCFG3
SSPIE
BCLIE
RCEN
Bit 3
RBIE
PSA
PD
—
—
—
S
CCP1IE
PCFG2
BRGH
Bit 2
T0IF
PEN
R/W
PS2
PORTE Data Direction Bits
—
—
Z
TMR2IE
PCFG1
RSEN
TRMT
Bit 1
INTF
POR
PS1
DC
UA
—
1999 Microchip Technology Inc.
TMR1IE
CCP2IE
PCFG0
TX9D
Bit 0
RBIF
BOR
SEN
PS0
BF
C
0000 0000 0000 0000
1111 1111 1111 1111
0000 0000 0000 0000
0001 1xxx 000q quuu
xxxx xxxx uuuu uuuu
--11 1111 --11 1111
1111 1111 1111 1111
1111 1111 1111 1111
1111 1111 1111 1111
0000 -111 0000 -111
---0 0000 ---0 0000
0000 000x 0000 000u
0000 0000 0000 0000
-r-0 0--0 -r-0 0--0
---- --qq ---- --uu
0000 0000 0000 0000
1111 1111 1111 1111
0000 0000 0000 0000
0000 0000 0000 0000
0000 -010 0000 -010
0000 0000 0000 0000
xxxx xxxx uuuu uuuu
0--- 0000
Value on:
POR,
BOR
—
—
—
—
—
—
—
—
—
0--- 0000
Value on
all other
resets
(2)
—
—
—
—
—
—
—
—
—