16F876 Microchip Technology, 16F876 Datasheet - Page 46
16F876
Manufacturer Part Number
16F876
Description
28/40-pin 8-Bit CMOS FLASH Microcontrollers
Manufacturer
Microchip Technology
Datasheet
1.16F876.pdf
(200 pages)
- Current page: 46 of 200
- Download datasheet (4Mb)
PIC16F87X
4.8
4.8.1
There are conditions when the device may not want to
write to the data EEPROM memory. To protect against
spurious EEPROM writes, various mechanisms have
been built-in. On power-up, the WREN bit is cleared.
Also, the Power-up Timer (72 ms duration) prevents
EEPROM write.
The write initiate sequence and the WREN bit together
help prevent an accidental write during brown-out,
power glitch, or software malfunction.
4.8.2
To protect against spurious writes to FLASH program
memory, the WRT bit in the configuration word may be
programmed to ‘0’ to prevent writes. The write initiate
sequence must also be followed. WRT and the config-
uration word cannot be programmed by user code, only
through the use of an external programmer.
TABLE 4-1:
TABLE 4-2:
DS30292B-page 46
Address
0Bh, 8Bh,
10Bh, 18Bh
10Dh
10Fh
10Ch
10Eh
18Ch
18Dh
8Dh
0Dh
Legend:
Note 1: These bits are reserved; always maintain these bits clear.
CP1
0
0
0
0
0
1
1
1
1
1
1
Configuration Bits
Protection Against Spurious Write
EEPROM DATA MEMORY
PROGRAM FLASH MEMORY
EEPROM access.
x = unknown, u = unchanged, r = reserved, - = unimplemented read as ’0’. Shaded cells are not used during FLASH/
INTCON
EEADR
EEADRH
EEDATA
EEDATH
EECON1
EECON2 EEPROM control resister2 (not a physical resister)
PIE2
PIR2
Name
CP0
0
1
1
1
1
0
0
0
0
1
1
READ/WRITE STATE OF INTERNAL FLASH PROGRAM MEMORY
REGISTERS ASSOCIATED WITH DATA EEPROM/PROGRAM FLASH
EEPROM address register
EEPROM data resister
EEPGD
Bit 7
GIE
—
—
—
—
WRT
x
0
0
1
1
0
0
1
1
0
1
Bit 6
PEIE
(1)
(1)
—
—
—
All program memory
Unprotected areas
Protected areas
Unprotected areas
Protected areas
Unprotected areas
Protected areas
Unprotected areas
Protected areas
All program memory
All program memory
Memory Location
EEPROM data resister high
Bit 5
T0IE
—
—
—
—
EEPROM address high
Bit 4
INTE
EEIE
EEIF
—
WRERR
BCLIE
BCLIF
Bit 3
RBIE
4.9
Each reprogrammable memory block has its own code
protect mechanism. External Read and Write opera-
tions are disabled if either of these mechanisms are
enabled.
4.9.1
The microcontroller itself can both read and write to the
internal Data EEPROM, regardless of the state of the
code protect configuration bit.
4.9.2
The microcontroller can read and execute instructions
out of the internal FLASH program memory, regardless
of the state of the code protect configuration bits. How-
ever the WRT configuration bit and the code protect bits
have different effects on writing to program memory.
Table 4-1 shows the various configurations and status
of reads and writes. To erase the WRT or code protec-
tion bits in the configuration word requires that the
device be fully erased.
Internal
WREN
Read
Bit 2
T0IF
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
—
—
Operation during Code Protect
DATA EEPROM MEMORY
PROGRAM FLASH MEMORY
Bit 1
INTF
WR
—
—
Internal
Write
Yes
Yes
Yes
No
No
No
No
No
No
No
No
CCP2IE
CCP2IF
Bit 0
RBIF
RD
1999 Microchip Technology Inc.
ICSP Read ICSP Write
0000 000x
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
x--- x000
-r-0 0--0
-r-0 0--0
Value on:
Yes
Yes
Yes
Yes
Yes
Yes
No
No
No
No
No
POR,
BOR
0000 000u
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
x--- u000
-r-0 0--0
-r-0 0--0
Value on
all other
resets
Yes
Yes
No
No
No
No
No
No
No
No
No
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