C8051F962-A-GM Silicon Labs, C8051F962-A-GM Datasheet - Page 107

• Manufacturer Part Number: C8051F962-A-GM
• Description: 8-bit Microcontrollers - MCU 128KB, DC-DC, AES DQFN76
• Manufacturer: Silicon Labs

Specifications of C8051F962-A-GM

• Rohs: yes
• Core: 8051
• Processor Series: C8051
• Data Bus Width: 8 bit
• Maximum Clock Frequency: 25 MHz
• Program Memory Size: 128 KB
• Data Ram Size: 8448 B
• On-chip Adc: Yes
• Operating Supply Voltage: 2.5 V to 3.3 V
• Operating Temperature Range: - 40 C to + 85 C
• Package / Case: DQFN-76
• Mounting Style: SMD/SMT
• Number Of Programmable I/os: 57
• Number Of Timers: 4

7.3. Comparator Response Time
Comparator response time may be configured in software via the CPTnMD registers described on
“CPT0MD: Comparator 0 Mode Selection” on page 109 and “CPT1MD: Comparator 1 Mode Selection” on
page 111. Four response time settings are available: Mode 0 (Fastest Response Time), Mode 1, Mode 2,
and Mode 3 (Lowest Power). Selecting a longer response time reduces the Comparator active supply cur-
rent. The Comparators also have low power shutdown state, which is entered any time the comparator is
disabled. Comparator rising edge and falling edge response times are typically not equal. See Table 4.16
on page 74 for complete comparator timing and supply current specifications.
7.4. Comparator Hysterisis
The Comparators feature software-programmable hysterisis that can be used to stabilize the comparator
output while a transition is occurring on the input. Using the CPTnCN registers, the user can program both
the amount of hysteresis voltage (referred to the input voltage) and the positive and negative-going sym-
metry of this hysteresis around the threshold voltage (i.e., the comparator negative input).
Figure 7.3 shows that when positive hysterisis is enabled, the comparator output does not transition from
logic 0 to logic 1 until the comparator positive input voltage has exceeded the threshold voltage by an
amount equal to the programmed hysterisis. It also shows that when negative hysterisis is enabled, the
comparator output does not transition from logic 1 to logic 0 until the comparator positive input voltage has
fallen below the threshold voltage by an amount equal to the programmed hysterisis.
The amount of positive hysterisis is determined by the settings of the CPnHYP bits in the CPTnCN register
and the amount of negative hysteresis voltage is determined by the settings of the CPnHYN bits in the
same register. Settings of 20 mV, 10 mV, 5 mV, or 0 mV can be programmed for both positive and negative
hysterisis. See Section “Table 4.16. Comparator Electrical Characteristics” on page 74 for complete com-
parator hysterisis specifications.
(Programmed with CP0HYP Bits)
Positive Hysteresis Voltage
INPUTS
OUTPUT
VIN+
VIN-
CIRCUIT CONFIGURATION
Positive Hysteresis
CPn+
CPn-
VIN+
VIN-
Disabled
V
OL
V
OH
+
_
CPn
Figure 7.3. Comparator Hysteresis Plot
Positive Hysteresis
Maximum
OUT
Rev. 0.5
Negative Hysteresis
Disabled
Negative Hysteresis
(Programmed by CP0HYN Bits)
Maximum
Negative Hysteresis Voltage
C8051F96x
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