C8051F962-A-GM Silicon Labs, C8051F962-A-GM Datasheet - Page 258

• Manufacturer Part Number: C8051F962-A-GM
• Description: 8-bit Microcontrollers - MCU 128KB, DC-DC, AES DQFN76
• Manufacturer: Silicon Labs

Specifications of C8051F962-A-GM

• Rohs: yes
• Core: 8051
• Processor Series: C8051
• Data Bus Width: 8 bit
• Maximum Clock Frequency: 25 MHz
• Program Memory Size: 128 KB
• Data Ram Size: 8448 B
• On-chip Adc: Yes
• Operating Supply Voltage: 2.5 V to 3.3 V
• Operating Temperature Range: - 40 C to + 85 C
• Package / Case: DQFN-76
• Mounting Style: SMD/SMT
• Number Of Programmable I/os: 57
• Number Of Timers: 4

C8051F96x
19.1. Normal Mode
The MCU is fully functional in Normal Mode. Figure 19.1 shows the on-chip power distribution to various
peripherals. There are three supply voltages powering various sections of the chip: VBAT, DCOUT, and the
1.8 V internal core supply (output of VREG0). All analog peripherals are directly powered from the VBAT
pin. All digital peripherals and the CIP-51 core are powered from the 1.8 V internal core supply (output of
VREG0). The Pulse counter, RAM, PMU0, and the SmaRTClock are powered from the internal core supply
when the device is in normal mode. The input to VREG0 is controlled by software and depends on the set-
tings of the power select switch. The power select switch may be configured to power VREG0 from VBAT
or from the output of the DC0.
19.2. Idle Mode
Setting the Idle Mode Select bit (PCON.0) causes the CIP-51 to halt the CPU and enter Idle mode as soon
as the instruction that sets the bit completes execution. All internal registers and memory maintain their
original data. All analog and digital peripherals can remain active during Idle mode.
Idle mode is terminated when an enabled interrupt is asserted or a reset occurs. The assertion of an
enabled interrupt will cause the Idle Mode Selection bit (PCON.0) to be cleared and the CPU to resume
operation. The pending interrupt will be serviced and the next instruction to be executed after the return
from interrupt (RETI) will be the instruction immediately following the one that set the Idle Mode Select bit.
If Idle mode is terminated by an internal or external reset, the CIP-51 performs a normal reset sequence
and begins program execution at address 0x0000.
If enabled, the Watchdog Timer (WDT) will eventually cause an internal watchdog reset and thereby termi-
nate the Idle mode. This feature protects the system from an unintended permanent shutdown in the event
258
VBATDC
GNDDC
SmaRTClock
Counter
PMU0
IND
Pulse
RAM
Converter
Buck
DC0
Figure 19.1. C8051F96x Power Distribution
VDC
1.9 V
Sleep
Power
Select
Stop/Suspend
Active/Idle/
VBAT
VREG0
Rev. 0.5
1.8 to 3.6 V
1.8 V
VIO/VIORF must be <= VBAT
M
U
A
X
Analog Peripherals
CIP-51
Digital Peripherals
Core
SENSOR
TEMP
VREF
ADC
Timers
Flash
AES
+
-
COMPARATORS
LCD
VOLTAGE
SMBus
UART
SPI
+
-
VIORF
VIO