C8051F962-A-GM Silicon Labs, C8051F962-A-GM Datasheet - Page 273

• Manufacturer Part Number: C8051F962-A-GM
• Description: 8-bit Microcontrollers - MCU 128KB, DC-DC, AES DQFN76
• Manufacturer: Silicon Labs

Specifications of C8051F962-A-GM

• Rohs: yes
• Core: 8051
• Processor Series: C8051
• Data Bus Width: 8 bit
• Maximum Clock Frequency: 25 MHz
• Program Memory Size: 128 KB
• Data Ram Size: 8448 B
• On-chip Adc: Yes
• Operating Supply Voltage: 2.5 V to 3.3 V
• Operating Temperature Range: - 40 C to + 85 C
• Package / Case: DQFN-76
• Mounting Style: SMD/SMT
• Number Of Programmable I/os: 57
• Number Of Timers: 4

SFR Definition 20.1. DC0CN: DC-DC Converter Control
SFR Page = 0x2; SFR Address = 0xB1
Name
Reset
Type
Bit
6:5 CLKDIV[1:0] DC
1:0
7
4
3
2
Bit
MINPW[1:0] DC
AD0CKINV ADC0 Clock Inversion (Clock Invert During Sync).
CLKSEL
CLKINV
CLKSEL
SYNC
Name
R
7
0
DC
Specifies the dc-dc converter clock source.
0: The dc-dc converter is clocked from its local oscillator.
1: The dc-dc converter is clocked from the system clock.
Divides the dc-dc converter clock when the system clock is selected as the clock
source for dc-dc converter. Ignored all other times.
00: The dc-dc converter clock is system clock divided by 1.
01: The dc-dc converter clock is system clock divided by 2.
10: The dc-dc converter clock is system clock divided by 4.
11: The dc-dc converter clock is system clock divided by 8.
Inverts the ADC0 SAR clock derived from the dc-dc converter clock when the SYNC
bit (DC0CN.3) is enabled. This bit is ignored when the SYNC bit is set to zero.
0: ADC0 SAR clock is inverted.
1: ADC0 SAR clock is not inverted.
DC
Inverts the system clock used as the input to the dc-dc clock divider.
0: The dc-dc converter clock is not inverted.
1: The dc-dc converter clock is inverted.
ADC0 Synchronization Enable.
When synchronization is enabled, the ADC0SC[4:0] bits in the ADC0CF register
must be set to 00000b.
0: The ADC is not synchronized to the dc-dc converter.
1: The ADC is synchronized to the dc-dc converter. ADC0 tracking is performed dur-
ing the longest quiet time of the dc-dc converter switching cycle and ADC0 SAR
clock is also synchronized to the dc-dc converter switching cycle.
Specifies the minimum pulse width.
00: Minimum pulse detection logic is disabled (no pulse skipping).
01: Minimum pulse width is 10 ns.
10: Minimum pulse width is 20 ns.
11: Minimum pulse width is 40 ns.
R/W
-
-
-
-
DC Converter Clock Source Select.
DC Clock Divider.
DC Converter Clock Invert.
DC Converter Minimum Pulse Width.
6
0
CLKDIV[1:0]
R/W
5
0
AD0CKINV
R/W
Rev. 0.5
4
0
Function
CLKINV
R/W
3
0
ILIMIT
R/W
2
0
C8051F96x
MIN_PW[1:0]
1
1
R/W
0
1
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