C8051F962-A-GM Silicon Labs, C8051F962-A-GM Datasheet - Page 194
C8051F962-A-GM
Manufacturer Part Number
C8051F962-A-GM
Description
8-bit Microcontrollers - MCU 128KB, DC-DC, AES DQFN76
Manufacturer
Silicon Labs
Datasheet
1.C8051F960-A-GQ.pdf
(492 pages)
Specifications of C8051F962-A-GM
Rohs
yes
Core
8051
Processor Series
C8051
Data Bus Width
8 bit
Maximum Clock Frequency
25 MHz
Program Memory Size
128 KB
Data Ram Size
8448 B
On-chip Adc
Yes
Operating Supply Voltage
2.5 V to 3.3 V
Operating Temperature Range
- 40 C to + 85 C
Package / Case
DQFN-76
Mounting Style
SMD/SMT
Number Of Programmable I/os
57
Number Of Timers
4
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C8051F96x
14.6.3.1. CBC Encryption using SFRs
If encrypting multiple blocks, this process may be repeated. It is not necessary reconfigure the AES mod-
ule for each block. When using Cipher Block Chaining the initialization vector is written to the AES0XIN sfr
for the first block only, as described. Additional blocks will chain the encrypted data from the previous
block.
194
First Configure AES Module for CBC Block Cipher Mode Encryption
Repeat alternating write sequence 16 times
Write remaining encryption key bytes to AES0KIN for 192-bit and 256-bit decryption only.
Wait on AES done interrupt or poll bit 5 of AES0BCFG.
Read 16 encrypted bytes from the AES0YOUT sfr.
Reset AES module by writing 0x00 to AES0BCFG.
Configure the AES Module data flow for XOR on input data by writing 0x01 to the AES0DCFG sfr.
Write key size to bits 1 and 0 of the AES0BCFG.
Configure the AES core for encryption by setting bit 2 of AES0BCFG.
Enable the AES core by setting bit 3 of AES0BCFG.
Write plaintext byte to AES0BIN.
Write initialization vector to AES0XIN
Write encryption key byte to AES0KIN.
Rev. 0.5
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