C8051F962-A-GM Silicon Labs, C8051F962-A-GM Datasheet - Page 344

• Manufacturer Part Number: C8051F962-A-GM
• Description: 8-bit Microcontrollers - MCU 128KB, DC-DC, AES DQFN76
• Manufacturer: Silicon Labs

Specifications of C8051F962-A-GM

• Rohs: yes
• Core: 8051
• Processor Series: C8051
• Data Bus Width: 8 bit
• Maximum Clock Frequency: 25 MHz
• Program Memory Size: 128 KB
• Data Ram Size: 8448 B
• On-chip Adc: Yes
• Operating Supply Voltage: 2.5 V to 3.3 V
• Operating Temperature Range: - 40 C to + 85 C
• Package / Case: DQFN-76
• Mounting Style: SMD/SMT
• Number Of Programmable I/os: 57
• Number Of Timers: 4

C8051F96x
26.4. Adjusting the VBAT Monitor Threshold
The VBAT Monitor is used primarily for the contrast control function, to detect when VBAT has fallen below
a specific threshold. The VBAT monitor threshold may be set independently of the contrast setting or it may
be linked to the contrast setting. When the VBAT monitor threshold is linked to the contrast setting, an off-
set (in 60mV steps) may be configured so that the VBAT monitor generates a VBAT low condition prior to
VBAT dropping below the programmed contrast voltage. The LCD0VBMCN register is used to enable and
configure the VBAT Monitor. The VBAT monitor may be enabled as a wake-up source to wake up the
device from Sleep mode when the battery is getting low. See the Power Management chapter for more
details.
SFR Definition 26.7. LCD0VBMCN: LCD0 VBAT Monitor Control
SFR Page = 0x2; SFR Address = 0xA6
344
Name VBATMEN OFFSET
Reset
Type
4:0
Bit
Bit
7
6
5
THRLD[4:0] VBAT Monitor Threshold
VBATMEN VBAT Monitor Enable
OFFSET
Unused
Name
R/W
7
0
The VBAT Monitor should be enabled in Contrast Control Mode 2, Mode 3, and
Mode 4.
0: The VBAT Monitor is disabled.
1: The VBAT Monitor is enabled.
VBAT Monitor Offset Enable
0: The VBAT Monitor Threshold is independent of the contrast setting.
1: The VBAT Monitor Threshold is linked to the contrast setting.
Read = 0. Write = Don’t Care.
If OFFSET is set to 0b, this bit field has the same defintion as the CNTRST bit field
and can be programmed independently of the contrast.
If OFFSET is set to 1b, this bit field is interpreted as an offset to the currently pro-
grammed contrast setting. The LCD0CNTRST register should be written before
setting OFFSET to logic 1 and should not be changed as long as VBAT Moni-
tor Offset is enabled. When THRLD[4:0] is set to 00000b, the VBAT monitor
threshold is equal to the contrast voltage. When THRLD[4:0] is set to 00001b, the
VBAT monitor threshold is one step higher than the contrast voltage. The step size
is equal to the step size of the CNTRST bit field.
R/W
6
0
R/W
5
0
Rev. 0.5
4
0
Function
3
0
THRLD[4:0]
R/W
2
0
1
0
0
0