C8051F962-A-GM Silicon Labs, C8051F962-A-GM Datasheet - Page 266

• Manufacturer Part Number: C8051F962-A-GM
• Description: 8-bit Microcontrollers - MCU 128KB, DC-DC, AES DQFN76
• Manufacturer: Silicon Labs

Specifications of C8051F962-A-GM

• Rohs: yes
• Core: 8051
• Processor Series: C8051
• Data Bus Width: 8 bit
• Maximum Clock Frequency: 25 MHz
• Program Memory Size: 128 KB
• Data Ram Size: 8448 B
• On-chip Adc: Yes
• Operating Supply Voltage: 2.5 V to 3.3 V
• Operating Temperature Range: - 40 C to + 85 C
• Package / Case: DQFN-76
• Mounting Style: SMD/SMT
• Number Of Programmable I/os: 57
• Number Of Timers: 4

C8051F96x
SFR Definition 19.5. PMU0FL: Power Management Unit Flag
SFR Page = 0x0; SFR Address = 0xB6
266
Notes:
Name
Reset
7:3
Bit
Type
2
1
0
Bit
1. The Low Power Internal Oscillator cannot be disabled and the MCU cannot be placed in suspend or sleep
2. PMU0 requires two system clocks to update the wake-up source flags after waking from suspend mode. The
mode if any wake-up flags are set to 1. Software should clear all wake-up sources after each reset and after
each wake-up from Suspend or Sleep Modes.
wake-up source flags will read 0 during the first two system clocks following the wake from suspend mode.
BATMWK
Reserved
CS0WK
Unused
Name
R
7
0
Unused
VBAT Monitor (inside
LCD Logic) Wake-up
Source Enable and Flag
Reserved
Pulse Counter Wake-up
Source Enable and Flag
R
6
0
Description
R
5
0
Rev. 0.5
Don’t Care.
0: Disable wake-up on
VBAT Monitor event.
1: Enable wake-up on CS0
event.
Must write 0.
0: Disable wake-up on
PC0 event.
1: Enable wake-up on PC0
event.
R
4
0
Write
R
3
0
BATMWK
R/W
2
0
1,2
0000000
Set to 1 if VBAT Monitor
event caused the last
wake-up.
Always reads 0.
Set to 1 if PC0 event
caused the last wake-up.
Reserved
R/W
1
0
Read
PC0WK
Varies
R/W
0