C8051F962-A-GM Silicon Labs, C8051F962-A-GM Datasheet - Page 13

• Manufacturer Part Number: C8051F962-A-GM
• Description: 8-bit Microcontrollers - MCU 128KB, DC-DC, AES DQFN76
• Manufacturer: Silicon Labs

Specifications of C8051F962-A-GM

• Rohs: yes
• Core: 8051
• Processor Series: C8051
• Data Bus Width: 8 bit
• Maximum Clock Frequency: 25 MHz
• Program Memory Size: 128 KB
• Data Ram Size: 8448 B
• On-chip Adc: Yes
• Operating Supply Voltage: 2.5 V to 3.3 V
• Operating Temperature Range: - 40 C to + 85 C
• Package / Case: DQFN-76
• Mounting Style: SMD/SMT
• Number Of Programmable I/os: 57
• Number Of Timers: 4

Figure 26.5. Contrast Control Mode 3 ................................................................... 339
Figure 26.6. Contrast Control Mode 4 ................................................................... 340
Figure 27.1. Port I/O Functional Block Diagram .................................................... 351
Figure 27.2. Port I/O Cell Block Diagram .............................................................. 352
Figure 27.3. Crossbar Priority Decoder with No Pins Skipped .............................. 356
Figure 27.4. Crossbar Priority Decoder with Crystal Pins Skipped ....................... 357
Figure 28.1. SMBus Block Diagram ...................................................................... 381
Figure 28.2. Typical SMBus Configuration ............................................................ 382
Figure 28.3. SMBus Transaction ........................................................................... 383
Figure 28.4. Typical SMBus SCL Generation ........................................................ 385
Figure 28.5. Typical Master Write Sequence ........................................................ 394
Figure 28.6. Typical Master Read Sequence ........................................................ 395
Figure 28.7. Typical Slave Write Sequence .......................................................... 396
Figure 28.8. Typical Slave Read Sequence .......................................................... 397
Figure 29.1. UART0 Block Diagram ...................................................................... 402
Figure 29.2. UART0 Baud Rate Logic ................................................................... 403
Figure 29.3. UART Interconnect Diagram ............................................................. 404
Figure 29.4. 8-Bit UART Timing Diagram .............................................................. 404
Figure 29.5. 9-Bit UART Timing Diagram .............................................................. 405
Figure 29.6. UART Multi-Processor Mode Interconnect Diagram ......................... 406
Figure 30.1. SPI Block Diagram ............................................................................ 411
Figure 30.2. Multiple-Master Mode Connection Diagram ...................................... 414
Figure 30.3. 3-Wire Single Master and 3-Wire Single Slave Mode 
Figure 30.4. 4-Wire Single Master Mode and 4-Wire Slave Mode 
Figure 30.5. Master Mode Data/Clock Timing ....................................................... 416
Figure 30.6. Slave Mode Data/Clock Timing (CKPHA = 0) ................................... 416
Figure 30.7. Slave Mode Data/Clock Timing (CKPHA = 1) ................................... 417
Figure 30.8. SPI Master Timing (CKPHA = 0) ....................................................... 421
Figure 30.9. SPI Master Timing (CKPHA = 1) ....................................................... 421
Figure 30.10. SPI Slave Timing (CKPHA = 0) ....................................................... 422
Figure 30.11. SPI Slave Timing (CKPHA = 1) ....................................................... 422
Figure 32.1. T0 Mode 0 Block Diagram ................................................................. 447
Figure 32.2. T0 Mode 2 Block Diagram ................................................................. 448
Figure 32.3. T0 Mode 3 Block Diagram ................................................................. 449
Figure 32.4. Timer 2 16-Bit Mode Block Diagram ................................................. 454
Figure 32.5. Timer 2 8-Bit Mode Block Diagram ................................................... 455
Figure 32.6. Timer 2 Capture Mode Block Diagram .............................................. 456
Figure 32.7. Timer 3 16-Bit Mode Block Diagram ................................................. 460
Figure 32.8. Timer 3 8-Bit Mode Block Diagram ................................................... 461
Figure 32.9. Timer 3 Capture Mode Block Diagram .............................................. 462
Figure 33.1. PCA Block Diagram ........................................................................... 466
Figure 33.2. PCA Counter/Timer Block Diagram ................................................... 468
Figure 33.3. PCA Interrupt Block Diagram ............................................................ 469
Connection Diagram .......................................................................... 414
Connection Diagram .......................................................................... 414
Rev. 0.5
C8051F96x
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