LPC1112FHN24/2021 NXP Semiconductors, LPC1112FHN24/2021 Datasheet - Page 110

• Manufacturer Part Number: LPC1112FHN24/2021
• Description: ARM Microcontrollers - MCU
• Manufacturer: NXP Semiconductors

Specifications of LPC1112FHN24/2021

• Rohs: yes
• Core: ARM Cortex M0
• Processor Series: LPC1112
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 2 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 1.8 V to 3.6 V
• Package / Case: HVQFN-24
• Mounting Style: SMD/SMT
• Factory Pack Quantity: 2450

NXP Semiconductors
Table 30.
LPC111X
Product data sheet
Document ID
LPC1111_12_13_14 v.5
Modifications:
LPC1111_12_13_14 v.4
Modifications:
LPC1111_12_13_14 v.3
Modifications:
LPC1111_12_13_14 v.2
Modifications:
LPC1111_12_13_14 v.1
Revision history
…continued
Release date
20110622
20110210
20101110
20100818
20100416
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ADC sampling frequency corrected in Table 7 (Table note 7).
Pull-up level specified in Table 3 to Table 4 and Section 7.7.1.
Parameter T
WWDT for parts LPC111x/102/202/302 added in Section 2 and Section 7.15.
Programmable open-drain mode for parts LPC111x/102/202/302 added in Section 2
and Section 7.12.
Condition for parameter T
Table note 4 of Table 5 updated.
Section 13 added.
Removed PLCC44 package information.
Power consumption graphs added for parts LPC111x/102/202/302 (Figure 13 to
Figure 17).
Parameter V
Typical value for parameter N
I
(minimum) for 2.0 V  V
Section 11.6 “ElectroMagnetic Compatibility (EMC)” added.
Power-up characterization added (Section 10.1 “Power-up ramp conditions”).
Parts LPC111x/102/202/302 added (LPC1100L series).
Power consumption data for parts LPC111x/102/202/302 added in Table 7.
PLL output frequency limited to 100 MHz in Section 7.15.2.
Description of RESET and WAKEUP functions updated in Section 6.
WDT description updated in Section 7.14. The WDT is a 24-bit timer.
Power profiles added to Section 2 and Section 7 for parts LPC111x/102/202/302.
V
t
Deep-sleep mode functionality changed to allow BOD and watchdog oscillator as the
only analog blocks allowed to remain running in Deep-sleep mode (Section 7.15.5.3).
V
Reset state of pins and start logic functionality added in Table 3 to Table 5.
Section 7.16.1 added.
Section “Memory mapping control” removed.
V
Section 9.4 added.
2
DS
ESD
DD
OH
C-bus pins configured as standard mode pins, parameter I
updated for SPI in master mode (Table 17).
range changed to 3.0 V  V
and I
All information provided in this document is subject to legal disclaimers.
limit changed to 6500 V (min) /+6500 V (max) in Table 6.
OH
Rev. 8 — 20 February 2013
cy(clk)
hys
Data sheet status
Product data sheet
Product data sheet
Product data sheet
Product data sheet
specifications updated for high-drive pins in Table 7.
Product data sheet
for I
corrected on Table 17.
2
C bus pins: typical value corrected V
DD
stg
 3.6 V.
in Table 5 updated.
endu
LPC1110/11/12/13/14/15
DD
added in Table 12 “Flash characteristics”.
 3.6 V in Table 15.
Change notice Supersedes
-
-
-
-
-
32-bit ARM Cortex-M0 microcontroller
LPC1111_12_13_14 v.4
LPC1111_12_13_14 v.3
LPC1111_12_13_14 v.2
LPC1111_12_13_14 v.1
-
hys
OL
= 0.05V
changed to 3.5 mA
© NXP B.V. 2013. All rights reserved.
DD
in Table 7.
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