LPC1112FHN24/2021 NXP Semiconductors, LPC1112FHN24/2021 Datasheet - Page 22

• Manufacturer Part Number: LPC1112FHN24/2021
• Description: ARM Microcontrollers - MCU
• Manufacturer: NXP Semiconductors

Specifications of LPC1112FHN24/2021

• Rohs: yes
• Core: ARM Cortex M0
• Processor Series: LPC1112
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 2 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 1.8 V to 3.6 V
• Package / Case: HVQFN-24
• Mounting Style: SMD/SMT
• Factory Pack Quantity: 2450

NXP Semiconductors
Table 6.
[1]
[2]
[3]
[4]
[5]
[6]
LPC111X
Product data sheet
Symbol
PIO1_4/AD5/
CT32B1_MAT3/
WAKEUP
PIO1_6/RXD/
CT32B0_MAT0
PIO1_7/TXD/
CT32B0_MAT1
PIO1_8/
CT16B1_CAP0
XTALIN
V
V
DD
SS
Pin state at reset for default function: I = Input; O = Output; PU = internal pull-up enabled (pins pulled up to full V
no pull-up/down enabled.
See
reset the chip and wake up from Deep power-down mode. An external pull-up resistor is required on this pin for the Deep power-down
mode.
Pad providing digital I/O functions with configurable pull-up/pull-down resistors and configurable hysteresis (see
I
Pad providing digital I/O functions with configurable pull-up/pull-down resistors, configurable hysteresis, and analog input. When
configured as a ADC input, digital section of the pad is disabled (see
When the system oscillator is not used, connect XTALIN and XTALOUT as follows: XTALIN can be left floating or can be grounded
(grounding is preferred to reduce susceptibility to noise). XTALOUT should be left floating.
2
C-bus pads compliant with the I
Figure 48
LPC1100L series: LPC1112 (HVQFN24 package)
for the reset pad configuration. RESET functionality is not available in Deep power-down mode. Use the WAKEUP pin to
HVQFN
pin
20
23
24
6
4
5; 22
3; 21
[3]
[6]
[5]
[3]
[3]
Start
logic
input
no
no
no
no
-
-
-
2
C-bus specification for I
Type
I/O
I
O
I
I/O
I
O
I/O
O
O
I/O
I
I
I
I
All information provided in this document is subject to legal disclaimers.
Rev. 8 — 20 February 2013
I; PU
I; PU
I; PU
I; PU
Reset
state
[1]
-
-
-
-
-
-
-
-
-
-
-
2
C standard mode and I
Description
PIO1_4 — General purpose digital input/output pin with 10 ns
glitch filter.
AD5 — A/D converter, input 5.
CT32B1_MAT3 — Match output 3 for 32-bit timer 1.
WAKEUP — Deep power-down mode wake-up pin with 20 ns
glitch filter. This pin must be pulled HIGH externally to enter
Deep power-down mode and pulled LOW to exit Deep
power-down mode. A LOW-going pulse as short as 50 ns
wakes up the part.
PIO1_6 — General purpose digital input/output pin.
RXD — Receiver input for UART.
CT32B0_MAT0 — Match output 0 for 32-bit timer 0.
PIO1_7 — General purpose digital input/output pin.
TXD — Transmitter output for UART.
CT32B0_MAT1 — Match output 1 for 32-bit timer 0.
PIO1_8 — General purpose digital input/output pin.
CT16B1_CAP0 — Capture input 0 for 16-bit timer 1.
Input to the oscillator circuit and internal clock generator
circuits. Input voltage must not exceed 1.8 V.
1.8 V supply voltage to the internal regulator, the external rail,
and the ADC. Also used as the ADC reference voltage.
Ground.
…continued
Figure
LPC1110/11/12/13/14/15
47).
2
C Fast-mode Plus.
32-bit ARM Cortex-M0 microcontroller
DD
© NXP B.V. 2013. All rights reserved.
Figure
level); IA = inactive,
47).
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