LPC1112FHN24/2021 NXP Semiconductors, LPC1112FHN24/2021 Datasheet - Page 49

• Manufacturer Part Number: LPC1112FHN24/2021
• Description: ARM Microcontrollers - MCU
• Manufacturer: NXP Semiconductors

Specifications of LPC1112FHN24/2021

• Rohs: yes
• Core: ARM Cortex M0
• Processor Series: LPC1112
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 2 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 1.8 V to 3.6 V
• Package / Case: HVQFN-24
• Mounting Style: SMD/SMT
• Factory Pack Quantity: 2450

NXP Semiconductors
LPC111X
Product data sheet
7.15.1 Features
7.16.1 Crystal oscillators
7.15 Windowed WatchDog Timer (LPC1100L and LPC1100XL series)
7.16 Clocking and power control
Remark: The windowed watchdog timer is available on the LPC1100L and LPC1100XL
series only.
The purpose of the watchdog is to reset the controller if software fails to periodically
service it within a programmable time window.
The LPC1110/11/12/13/14/15 include three independent oscillators. These are the system
oscillator, the Internal RC oscillator (IRC), and the Watchdog oscillator. Each oscillator can
be used for more than one purpose as required in a particular application.
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Enabled by software but requires a hardware reset or a watchdog reset/interrupt to be
disabled.
Incorrect/Incomplete feed sequence causes reset/interrupt if enabled.
Flag to indicate watchdog reset.
Programmable 24-bit timer with internal prescaler.
Selectable time period from (T
multiples of T
The Watchdog Clock (WDCLK) source can be selected from the Internal RC oscillator
(IRC), the Watchdog oscillator, or the main clock. This gives a wide range of potential
timing choices of Watchdog operation under different power reduction conditions. It
also provides the ability to run the WDT from an entirely internal source that is not
dependent on an external crystal and its associated components and wiring for
increased reliability.
Internally resets chip if not periodically reloaded during the programmable time-out
period.
Optional windowed operation requires reload to occur between a minimum and
maximum time period, both programmable.
Optional warning interrupt can be generated at a programmable time prior to
watchdog time-out.
Enabled by software but requires a hardware reset or a watchdog reset/interrupt to be
disabled.
Incorrect feed sequence causes reset or interrupt if enabled.
Flag to indicate watchdog reset.
Programmable 24-bit timer with internal prescaler.
Selectable time period from (T
multiples of T
The Watchdog Clock (WDCLK) source can be selected from the IRC or the dedicated
watchdog oscillator (WDO). This gives a wide range of potential timing choices of
watchdog operation under different power conditions.
All information provided in this document is subject to legal disclaimers.
cy(WDCLK)
cy(WDCLK)
Rev. 8 — 20 February 2013
 4.
 4.
cy(WDCLK)
cy(WDCLK)
LPC1110/11/12/13/14/15
 256  4) to (T
 256  4) to (T
32-bit ARM Cortex-M0 microcontroller
cy(WDCLK)
cy(WDCLK)
 2
 2
© NXP B.V. 2013. All rights reserved.
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24
 4) in
 4) in
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