LPC1112FHN24/2021 NXP Semiconductors, LPC1112FHN24/2021 Datasheet - Page 47

• Manufacturer Part Number: LPC1112FHN24/2021
• Description: ARM Microcontrollers - MCU
• Manufacturer: NXP Semiconductors

Specifications of LPC1112FHN24/2021

• Rohs: yes
• Core: ARM Cortex M0
• Processor Series: LPC1112
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 2 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 1.8 V to 3.6 V
• Package / Case: HVQFN-24
• Mounting Style: SMD/SMT
• Factory Pack Quantity: 2450

NXP Semiconductors
LPC111X
Product data sheet
7.10.1 Features
7.11.1 Features
7.10 I
7.11 10-bit ADC
The LPC1110/11/12/13/14/15 contain one I
Remark: Part LPC1112FDH20/102 does not contain the I
The I
(SCL) and a Serial DAta line (SDA). Each device is recognized by a unique address and
can operate as either a receiver-only device (e.g., an LCD driver) or a transmitter with the
capability to both receive and send information (such as memory). Transmitters and/or
receivers can operate in either master or slave mode, depending on whether the chip has
to initiate a data transfer or is only addressed. The I
controlled by more than one bus master connected to it.
The LPC1110/11/12/13/14/15 contain one ADC. It is a single 10-bit successive
approximation ADC with eight channels.
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C-bus serial I/O controller
Master or slave operation
8-frame FIFOs for both transmit and receive
4-bit to 16-bit frame
The I
I
Easy to configure as master, slave, or master/slave.
Programmable clocks allow versatile rate control.
Bidirectional data transfer between masters and slaves.
Multi-master bus (no central master).
Arbitration between simultaneously transmitting masters without corruption of serial
data on the bus.
Serial clock synchronization allows devices with different bit rates to communicate via
one serial bus.
Serial clock synchronization can be used as a handshake mechanism to suspend and
resume serial transfer.
The I
The I
10-bit successive approximation ADC.
Input multiplexing among 8 pins.
Power-down mode.
Measurement range 0 V to V
10-bit conversion time  2.44 s (up to 400 kSamples/s).
Burst conversion mode for single or multiple inputs.
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C-bus interface also supports Fast-mode Plus with bit rates up to 1 Mbit/s.
C-bus is bidirectional for inter-IC control using only two wires: a Serial Clock Line
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C-interface is a standard I
C-bus can be used for test and diagnostic purposes.
C-bus controller supports multiple address recognition and a bus monitor mode.
All information provided in this document is subject to legal disclaimers.
Rev. 8 — 20 February 2013
DD
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2
C-bus compliant interface with open-drain pins. The
LPC1110/11/12/13/14/15
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C-bus controller.
32-bit ARM Cortex-M0 microcontroller
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C is a multi-master bus and can be
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C-bus controller.
© NXP B.V. 2013. All rights reserved.
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