LPC1112FHN24/2021 NXP Semiconductors, LPC1112FHN24/2021 Datasheet - Page 20

• Manufacturer Part Number: LPC1112FHN24/2021
• Description: ARM Microcontrollers - MCU
• Manufacturer: NXP Semiconductors

Specifications of LPC1112FHN24/2021

• Rohs: yes
• Core: ARM Cortex M0
• Processor Series: LPC1112
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 2 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 1.8 V to 3.6 V
• Package / Case: HVQFN-24
• Mounting Style: SMD/SMT
• Factory Pack Quantity: 2450

NXP Semiconductors
Table 5.
[1]
[2]
[3]
[4]
[5]
Table 6.
LPC111X
Product data sheet
Symbol
XTALOUT
V
V
Symbol
RESET/PIO0_0
PIO0_1/CLKOUT/
CT32B0_MAT2
PIO0_2/SSEL0/
CT16B0_CAP0
PIO0_4/SCL
PIO0_5/SDA
PIO0_6/SCK0
SS
SSA
Pin state at reset for default function: I = Input; O = Output; PU = internal pull-up enabled (pins pulled up to full V
no pull-up/down enabled.
See
reset the chip and wake up from Deep power-down mode. An external pull-up resistor is required on this pin for the Deep power-down
mode.
5 V tolerant pad providing digital I/O functions with configurable pull-up/pull-down resistors and configurable hysteresis (see
5 V tolerant pad providing digital I/O functions with configurable pull-up/pull-down resistors, configurable hysteresis, and analog input.
When configured as a ADC input, digital section of the pad is disabled and the pin is not 5 V tolerant (see
When the system oscillator is not used, connect XTALIN and XTALOUT as follows: XTALIN can be left floating or can be grounded
(grounding is preferred to reduce susceptibility to noise). XTALOUT should be left floating.
Figure 48
LPC1100L series: LPC1112 pin description table (TSSOP20 with V
LPC1100L series: LPC1112 (HVQFN24 package)
for the reset pad configuration. RESET functionality is not available in Deep power-down mode. Use the WAKEUP pin to
13
16
6
HVQFN
pin
1
2
7
8
9
10
[2]
[3]
[3]
[4]
[4]
[3]
[5]
Start
logic
input
yes
yes
yes
yes
yes
yes
Start
logic
input
-
-
-
I/O
I/O
Type
I
I/O
I/O
O
O
I/O
I/O
I
I/O
I/O
I/O
I/O
All information provided in this document is subject to legal disclaimers.
Type
O
I
I
Rev. 8 — 20 February 2013
I; IA
I; IA
Reset
state
[1]
I; PU
-
I; PU
-
-
I; PU
-
-
-
-
I; PU
-
Reset
state
[1]
-
-
-
Description
RESET — External reset input with 20 ns glitch filter. A
LOW-going pulse as short as 50 ns on this pin resets the
device, causing I/O ports and peripherals to take on their
default states, and processor execution to begin at address 0.
PIO0_0 — General purpose digital input/output pin with 10 ns
glitch filter.
PIO0_1 — General purpose digital input/output pin. A LOW
level on this pin during reset starts the ISP command handler.
CLKOUT — Clockout pin.
CT32B0_MAT2 — Match output 2 for 32-bit timer 0.
PIO0_2 — General purpose digital input/output pin.
SSEL0 — Slave Select for SPI0.
CT16B0_CAP0 — Capture input 0 for 16-bit timer 0.
PIO0_4 — General purpose digital input/output pin
(open-drain).
SCL — I
sink only if I
configuration register.
PIO0_5 — General purpose digital input/output pin
(open-drain).
SDA — I
sink only if I
configuration register.
PIO0_6 — General purpose digital input/output pin.
SCK0 — Serial clock for SPI0.
Description
Output from the oscillator amplifier.
Ground.
Analog ground.
LPC1110/11/12/13/14/15
2
2
C-bus, open-drain clock input/output. High-current
C-bus, open-drain data input/output. High-current
2
2
C Fast-mode Plus is selected in the I/O
C Fast-mode Plus is selected in the I/O
32-bit ARM Cortex-M0 microcontroller
DDA
and V
SSA
pins)
Figure
…continued
DD
© NXP B.V. 2013. All rights reserved.
47).
level ); IA = inactive,
Figure
20 of 114
47).