LPC1112FHN24/2021 NXP Semiconductors, LPC1112FHN24/2021 Datasheet - Page 87

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LPC1112FHN24/2021

Manufacturer Part Number
LPC1112FHN24/2021
Description
ARM Microcontrollers - MCU
Manufacturer
NXP Semiconductors
Datasheet

Specifications of LPC1112FHN24/2021

Rohs
yes
Core
ARM Cortex M0
Processor Series
LPC1112
Data Bus Width
32 bit
Maximum Clock Frequency
50 MHz
Program Memory Size
16 KB
Data Ram Size
2 KB
On-chip Adc
Yes
Operating Supply Voltage
1.8 V to 3.6 V
Package / Case
HVQFN-24
Mounting Style
SMD/SMT
Factory Pack Quantity
2450
NXP Semiconductors
11. Application information
LPC111X
Product data sheet
11.1 ADC usage notes
11.2 Use of ADC input trigger signals
11.3 XTAL input
The following guidelines show how to increase the performance of the ADC in a noisy
environment beyond the ADC specifications listed in
For applications that use trigger signals to start conversions and require a precise sample
frequency, ensure that the period of the trigger signal is an integral multiple of the period
of the ADC clock.
The input voltage to the on-chip oscillators is limited to 1.8 V. If the oscillator is driven by a
clock in slave mode, it is recommended that the input be coupled through a capacitor with
C
capacitor to ground C
mode, a minimum of 200 mV (RMS) is needed.
In slave mode the input clock signal should be coupled by means of a capacitor of 100 pF
(Figure
corresponds to a square wave signal with a signal swing of between 280 mV and 1.4 V.
The XTALOUT pin in this configuration can be left unconnected.
External components and models used in oscillation mode are shown in
Table 26
and the capacitances C
Fig 45. Slave mode operation of the on-chip oscillator
i
= 100 pF. To limit the input voltage to the specified range, choose an additional
The ADC input trace must be short and as close as possible to the
LPC1110/11/12/13/14/15 chip.
The ADC input traces must be shielded from fast switching digital signals and noisy
power supply lines.
Because the ADC and the digital core share the same power supply, the power supply
line must be adequately filtered.
To improve the ADC performance in a very noisy environment, put the device in Sleep
mode during the ADC conversion.
45), with an amplitude between 200 mV (RMS) and 1000 mV (RMS). This
and
Table
All information provided in this document is subject to legal disclaimers.
27. Since the feedback resistance is integrated on chip, only a crystal
g
Rev. 8 — 20 February 2013
which attenuates the input voltage by a factor C
X1
and C
X2
need to be connected externally in case of
XTALIN
LPC1xxx
C i
100 pF
LPC1110/11/12/13/14/15
002aae788
32-bit ARM Cortex-M0 microcontroller
C g
Table
14:
i
/(C
© NXP B.V. 2013. All rights reserved.
Figure 46
i
+ C
g
). In slave
87 of 114
and in

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