LPC1112FHN24/2021 NXP Semiconductors, LPC1112FHN24/2021 Datasheet - Page 51

• Manufacturer Part Number: LPC1112FHN24/2021
• Description: ARM Microcontrollers - MCU
• Manufacturer: NXP Semiconductors

Specifications of LPC1112FHN24/2021

• Rohs: yes
• Core: ARM Cortex M0
• Processor Series: LPC1112
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 2 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 1.8 V to 3.6 V
• Package / Case: HVQFN-24
• Mounting Style: SMD/SMT
• Factory Pack Quantity: 2450

NXP Semiconductors
LPC111X
Product data sheet
7.16.1.3 Watchdog oscillator
7.16.5.1 Power profiles (LPC1100L and LPC1100XL series only)
7.16.2 System PLL
7.16.3 Clock output
7.16.4 Wake-up process
7.16.5 Power control
The system oscillator operates at frequencies of 1 MHz to 25 MHz. This frequency can be
boosted to a higher frequency, up to the maximum CPU operating frequency, by the
system PLL.
The watchdog oscillator can be used as a clock source that directly drives the CPU, the
watchdog timer, or the CLKOUT pin. The watchdog oscillator nominal frequency is
programmable between 9.4 kHz and 2.3 MHz. The frequency spread over processing and
temperature is 40 %.
The PLL accepts an input clock frequency in the range of 10 MHz to 25 MHz. The input
frequency is multiplied up to a high frequency with a Current Controlled Oscillator (CCO).
The multiplier can be an integer value from 1 to 32. The CCO operates in the range of
156 MHz to 320 MHz, so there is an additional divider in the loop to keep the CCO within
its frequency range while the PLL is providing the desired output frequency. The PLL
output frequency must be lower than 100 MHz. The output divider may be set to divide by
2, 4, 8, or 16 to produce the output clock. Since the minimum output divider value is 2, it is
insured that the PLL output has a 50 % duty cycle. The PLL is turned off and bypassed
following a chip reset and may be enabled by software. The program must configure and
activate the PLL, wait for the PLL to lock, and then connect to the PLL as a clock source.
The PLL settling time is 100 s.
The LPC1110/11/12/13/14/15 features a clock output function that routes the IRC
oscillator, the system oscillator, the watchdog oscillator, or the main clock to an output pin.
The LPC1110/11/12/13/14/15 begin operation at power-up and when awakened from
Deep power-down mode by using the 12 MHz IRC oscillator as the clock source. This
allows chip operation to resume quickly. If the system oscillator or the PLL is needed by
the application, software will need to enable these features and wait for them to stabilize
before they are used as a clock source.
The LPC1110/11/12/13/14/15 support a variety of power control features. There are three
special modes of processor power reduction: Sleep mode, Deep-sleep mode, and Deep
power-down mode. The CPU clock rate may also be controlled as needed by changing
clock sources, reconfiguring PLL values, and/or altering the CPU clock divider value. This
allows a trade-off of power versus processing speed based on application requirements.
In addition, a register is provided for shutting down the clocks to individual on-chip
peripherals, allowing fine tuning of power consumption by eliminating all dynamic power
use in any peripherals that are not required for the application. Selected peripherals have
their own clock divider which provides even better power control.
The power consumption in Active and Sleep modes can be optimized for the application
through simple calls to the power profile. The power configuration routine configures the
LPC1110/11/12/13/14/15 for one of the following power modes:
All information provided in this document is subject to legal disclaimers.
Rev. 8 — 20 February 2013
LPC1110/11/12/13/14/15
32-bit ARM Cortex-M0 microcontroller
© NXP B.V. 2013. All rights reserved.
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