MT48V8M16LFB4-8:G Micron Technology Inc, MT48V8M16LFB4-8:G Datasheet - Page 23

• Manufacturer Part Number: MT48V8M16LFB4-8:G
• Description: IC SDRAM 128MBIT 125MHZ 54VFBGA
• Manufacturer: Micron Technology Inc
• Type: Mobile SDRAMr

Specifications of MT48V8M16LFB4-8:G

• Format - Memory: RAM
• Memory Type: Mobile SDRAM
• Memory Size: 128M (8Mx16)
• Speed: 125MHz
• Interface: Parallel
• Voltage - Supply: 2.3 V ~ 2.7 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 54-VFBGA
• Organization: 8Mx16
• Density: 128Mb
• Address Bus: 14b
• Access Time (max): 19/8/7ns
• Maximum Clock Rate: 125MHz
• Operating Supply Voltage (typ): 2.5V
• Package Type: VFBGA
• Operating Temp Range: 0C to 70C
• Operating Supply Voltage (max): 2.7V
• Operating Supply Voltage (min): 2.3V
• Supply Current: 100mA
• Pin Count: 54
• Mounting: Surface Mount
• Operating Temperature Classification: Commercial
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Commands
Table 8:
COMMAND INHIBIT
NO OPERATION (NOP)
PDF: 09005aef807f4885/Source: 09005aef8071a76b
128Mbx16x32Mobile_2.fm - Rev. M 1/09 EN
Name (Function)
COMMAND INHIBIT (NOP)
NO OPERATION (NOP)
ACTIVE (Select bank and activate row)
READ (Select bank and column, and start READ burst)
WRITE (Select bank and column, and start WRITE burst)
BURST TERMINATE
PRECHARGE (Deactivate row in bank or banks)
AUTO REFRESH or SELF REFRESH
(Enter self refresh mode)
LOAD MODE REGISTER
Write enable/output enable
Write inhibit/output High-Z
Truth Table – Commands and DQM Operation
Note 1 applies to entire table
Notes:
Table 8 provides a quick reference of available commands. This is followed by a written
description of each command. Three additional Truth Tables appear following the Oper-
ation section; these tables provide current state/next state information.
1. CKE is HIGH for all commands shown except SELF REFRESH.
2. A0–A11 provide row address, and BA0, BA1 determine which bank is made active.
3. A0–A8 (x16) or A0–A7 (x32) provide column address; A10 HIGH enables the auto precharge
4. A10 LOW: BA0, BA1 determine the bank being precharged. A10 HIGH: All banks precharged
5. This command is AUTO REFRESH if CKE is HIGH, SELF REFRESH if CKE is LOW.
6. Internal refresh counter controls row addressing; all inputs and I/Os are “Don’t Care” except
7. A0–A10 define the op-code written to the mode register. BA0–BA1 either select mode regis-
8. Activates or deactivates the DQ during WRITEs (0-clock delay) and READs (2-clock delay). For
The COMMAND INHIBIT function prevents new commands from being executed by the
SDRAM, regardless of whether the CLK signal is enabled. The SDRAM is effectively dese-
lected. Operations already in progress are not affected.
The NO OPERATION (NOP) command is used to instruct the selected SDRAM to
perform a NOP (RAS#, CAS#, and WE# are HIGH, and CS# is LOW). This prevents
unwanted commands from being registered during idle or wait states. Operations
already in progress are not affected.
feature (nonpersistent), while A10 LOW disables the auto precharge feature; BA0, BA1
determine which bank is being read from or written to.
and BA0, BA1 are “Don’t Care.”
for CKE.
ter or the extended mode register (BA0 = BA1 = 0 select the mode register, BA1 = 1, BA0 = 0
selects the extended mode register, all other combinations of BA0-BA1 are reserved).
x16, LDQM controls DQ0–DQ7, and UDQM controls DQ8–DQ15. For x32, DQM0 controls
DQ0–DQ7, DQM1 controls DQ8–DQ15, DQM2 controls DQ16–23, and DQM3 controls DQ24–
DQ31.
CS# RAS# CAS# WE# DQM
H
L
L
L
L
L
L
L
L
–
–
23
H
H
H
H
X
L
L
L
L
–
–
Micron Technology, Inc., reserves the right to change products or specifications without notice.
H
H
H
H
X
L
L
L
L
–
–
128Mb: x16, x32 Mobile SDRAM
H
H
H
H
X
L
L
L
L
–
–
L/H
L/H
H
X
X
X
X
X
X
X
L
8
8
Bank/row
Bank/col
Bank/col
Op-code
©2001 Micron Technology, Inc. All rights reserved.
Addr
Register Definition
Code
X
X
X
X
–
–
High-Z
Active
Active
Valid
DQ
X
X
X
X
X
X
X
Notes
5, 6
2
3
3
4
7
8
8