MT48V8M16LFB4-8:G Micron Technology Inc, MT48V8M16LFB4-8:G Datasheet - Page 28

• Manufacturer Part Number: MT48V8M16LFB4-8:G
• Description: IC SDRAM 128MBIT 125MHZ 54VFBGA
• Manufacturer: Micron Technology Inc
• Type: Mobile SDRAMr

Specifications of MT48V8M16LFB4-8:G

• Format - Memory: RAM
• Memory Type: Mobile SDRAM
• Memory Size: 128M (8Mx16)
• Speed: 125MHz
• Interface: Parallel
• Voltage - Supply: 2.3 V ~ 2.7 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 54-VFBGA
• Organization: 8Mx16
• Density: 128Mb
• Address Bus: 14b
• Access Time (max): 19/8/7ns
• Maximum Clock Rate: 125MHz
• Operating Supply Voltage (typ): 2.5V
• Package Type: VFBGA
• Operating Temp Range: 0C to 70C
• Operating Supply Voltage (max): 2.7V
• Operating Supply Voltage (min): 2.3V
• Supply Current: 100mA
• Pin Count: 54
• Mounting: Surface Mount
• Operating Temperature Classification: Commercial
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Figure 13:
PDF: 09005aef807f4885/Source: 09005aef8071a76b
128Mbx16x32Mobile_2.fm - Rev. M 1/09 EN
CAS Latency
Upon completion of a burst, assuming no other commands have been initiated, the DQ
will go High-Z. A full-page burst will continue until terminated. (At the end of the page, it
will wrap to column 0 and continue.)
Data from any READ burst may be truncated with a subsequent READ command, and
data from a fixed-length READ burst may be immediately followed by data from a READ
command. In either case, a continuous flow of data can be maintained. The first data
element from the new burst either follows the last element of a completed burst or the
last desired data element of a longer burst that is being truncated. The new READ
command should be issued x cycles before the clock edge at which the last desired data
element is valid, where x = CL - 1.
COMMAND
COMMAND
COMMAND
This is shown in Figure 14 on page 29 for CL = 2 and CL = 3; data element n + 3 is either
the last of a burst of four or the last desired of a longer burst. The 128Mb SDRAM uses a
pipelined architecture and, therefore, does not require the 2n rule associated with a
prefetch architecture. A READ command can be initiated on any clock cycle following a
previous READ command. Full-speed random read accesses can be performed to the
same bank, as shown in Figure 15 on page 30, or each subsequent READ may be
performed to a different bank.
CLK
CLK
CLK
DQ
DQ
DQ
READ
READ
READ
T0
T0
T0
t
t AC
LZ
CL = 1
CL = 2
NOP
NOP
T1
NOP
T1
T1
t
t AC
LZ
D
t OH
OUT
CL = 3
28
T2
NOP
T2
NOP
T2
t
t AC
LZ
D
t OH
Micron Technology, Inc., reserves the right to change products or specifications without notice.
OUT
128Mb: x16, x32 Mobile SDRAM
T3
T3
NOP
D
t OH
OUT
DON’T CARE
UNDEFINED
T4
©2001 Micron Technology, Inc. All rights reserved.
READs