LPC1343FHN33,551 NXP Semiconductors, LPC1343FHN33,551 Datasheet - Page 131
LPC1343FHN33,551
Manufacturer Part Number
LPC1343FHN33,551
Description
IC MCU 32BIT 32KB FLASH 33HVQFN
Manufacturer
NXP Semiconductors
Series
LPC13xxr
Specifications of LPC1343FHN33,551
Program Memory Type
FLASH
Program Memory Size
32KB (32K x 8)
Package / Case
33-VQFN Exposed Pad, 33-HVQFN, 33-SQFN, 33-DHVQFN
Core Processor
ARM® Cortex-M3™
Core Size
32-Bit
Speed
72MHz
Connectivity
I²C, Microwire, SPI, SSI, SSP, UART/USART, USB
Peripherals
Brown-out Detect/Reset, POR, WDT
Number Of I /o
28
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
2 V ~ 3.6 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
LPC13
Core
ARM Cortex M3
Data Bus Width
32 bit
Data Ram Size
8 KB
Interface Type
I2C, UART
Maximum Clock Frequency
72 MHz
Number Of Programmable I/os
28
Number Of Timers
4
Operating Supply Voltage
3.3 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2, KSK-LPC1343
Development Tools By Supplier
OM11039, OM11040, OM11046, OM11048
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 8 Channel
Package
33HVQFN EP
Device Core
ARM Cortex M3
Family Name
LPC1000
Maximum Speed
72 MHz
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
568-4944
935289655551
935289655551
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LPC1343FHN33,551
Manufacturer:
NXP
Quantity:
780
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NXP Semiconductors
Table 155. USB Device Interrupt registers bit allocation
UM10375
User manual
Bit
Symbol
Bit
Symbol
Bit
Symbol
Bit
Symbol
9.10.1.1 USB Device Interrupt Status register (USBDevIntSt - 0x4002 0000)
9.10.1 Device interrupt registers
15
EP6
-
31
23
7
-
-
Table 154. Register overview: USB device (base address 0x4002 0000)
[1]
[2]
Table 155
USBDevIntEn, and USBDevIntClr.
The USBDevIntSt register holds the status of each interrupt whether it is enabled or not. A
0 indicates no interrupt and 1 indicates the presence of the interrupt. USBDevIntSt is a
read only register.
Name
Device interrupt registers
USBDevIntSt
USBDevIntEn
USBDevIntClr
USBDevIntSet
SIE command registers
USBCmdCode
USBCmdData
USB data transfer registers
USBRxData
USBTxData
USBRxPLen
USBTxPLen
USBCtrl
Miscellaneous registers
USBDevFIQSel
14
Reset value reflects the data stored in used bits only. It does not include reserved bits content.
Reading WO register will return an invalid value.
-
EP5
30
22
6
-
-
shows the bit allocation for the device interrupt registers USBDevIntSt,
TxENDPKT
13
All information provided in this document is subject to legal disclaimers.
EP4
29
21
5
-
-
Access
RO
R/W
WO
WO
WO
RO
RO
WO
RO
WO
R/W
WO
Rev. 2 — 7 July 2010
RxENDPKT
[2]
[2]
[2]
[2]
[2]
[2]
12
EP3
Address
offset
0x00
0x04
0x08
0x0C
0x10
0x14
0x18
0x1C
0x20
0x24
0x28
0x2C
28
20
4
-
-
CD_FULL
Description
USB Device Interrupt Status
USB Device Interrupt Enable
USB Device Interrupt Clear
USB Device Interrupt Set
USB Command Code
USB Command Data
USB Receive Data
USB Transmit Data
USB Receive Packet Length
USB Transmit Packet Length
USB Control
USB Device FIQ select
11
Chapter 9: LPC13xx USB device controller
EP2
27
19
3
-
-
CC_EMPTY
10
EP1
26
18
2
-
-
DEV_STAT
EP0
25
17
UM10375
9
1
-
-
© NXP B.V. 2010. All rights reserved.
Reset value
0x0000 0010
0x0000 0000
0x0000 0000
0x0000 0000
0x0000 0000
0x0000 0000
0x0000 0000
0x0000 0000
0x0000 0000
0x0000 0000
0x0000 0000
0x00
FRAME
133 of 333
EP7
24
16
8
0
-
-
[1]
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