LPC1343FHN33,551 NXP Semiconductors, LPC1343FHN33,551 Datasheet - Page 325
LPC1343FHN33,551
Manufacturer Part Number
LPC1343FHN33,551
Description
IC MCU 32BIT 32KB FLASH 33HVQFN
Manufacturer
NXP Semiconductors
Series
LPC13xxr
Specifications of LPC1343FHN33,551
Program Memory Type
FLASH
Program Memory Size
32KB (32K x 8)
Package / Case
33-VQFN Exposed Pad, 33-HVQFN, 33-SQFN, 33-DHVQFN
Core Processor
ARM® Cortex-M3™
Core Size
32-Bit
Speed
72MHz
Connectivity
I²C, Microwire, SPI, SSI, SSP, UART/USART, USB
Peripherals
Brown-out Detect/Reset, POR, WDT
Number Of I /o
28
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
2 V ~ 3.6 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
LPC13
Core
ARM Cortex M3
Data Bus Width
32 bit
Data Ram Size
8 KB
Interface Type
I2C, UART
Maximum Clock Frequency
72 MHz
Number Of Programmable I/os
28
Number Of Timers
4
Operating Supply Voltage
3.3 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2, KSK-LPC1343
Development Tools By Supplier
OM11039, OM11040, OM11046, OM11048
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 8 Channel
Package
33HVQFN EP
Device Core
ARM Cortex M3
Family Name
LPC1000
Maximum Speed
72 MHz
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
568-4944
935289655551
935289655551
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LPC1343FHN33,551
Manufacturer:
NXP
Quantity:
780
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NXP Semiconductors
3.10.4
Chapter 4: LPC13xx Power Management Unit (PMU)
4.1
4.2
4.2.1
Chapter 5: LPC13xx Interrupt controller
5.1
5.2
5.3
5.4
5.5
5.6
5.6.1
5.6.2
5.6.3
5.6.4
5.6.5
5.6.6
5.6.7
5.6.8
5.6.9
Chapter 6: LPC13xx I/O configuration
6.1
6.2
6.3
6.3.1
6.3.2
6.3.3
Chapter 7: LPC13xx Pin configuration
7.1
7.2
7.3
Chapter 8: LPC13xx General Purpose I/O (GPIO)
8.1
8.2
8.3
8.4
8.4.1
8.4.2
8.4.3
8.4.4
8.4.5
8.4.6
UM10375
User manual
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Register description . . . . . . . . . . . . . . . . . . . . 51
How to read this chapter . . . . . . . . . . . . . . . . . 53
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Interrupt sources . . . . . . . . . . . . . . . . . . . . . . . 53
Vector table remapping . . . . . . . . . . . . . . . . . . 55
Register description . . . . . . . . . . . . . . . . . . . . 56
How to read this chapter . . . . . . . . . . . . . . . . . 77
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
General description . . . . . . . . . . . . . . . . . . . . . 77
How to read this chapter . . . . . . . . . . . . . . . . 108
LPC134x pin configuration . . . . . . . . . . . . . . 109
LPC131x pin configuration . . . . . . . . . . . . . . 111
How to read this chapter . . . . . . . . . . . . . . . . 119
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
Pin description . . . . . . . . . . . . . . . . . . . . . . . . 119
Register description . . . . . . . . . . . . . . . . . . . 119
Post divider . . . . . . . . . . . . . . . . . . . . . . . . . . . .48
Feedback divider . . . . . . . . . . . . . . . . . . . . . . .48
Changing the divider values . . . . . . . . . . . . . . .48
Frequency selection . . . . . . . . . . . . . . . . . . . . 49
Power control register. . . . . . . . . . . . . . . . . . . 51
Example:. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55
Interrupt Clear-Enable Register 0 . . . . . . . . . . 60
Interrupt Active Bit Register 0 . . . . . . . . . . . . . 67
Pin function. . . . . . . . . . . . . . . . . . . . . . . . . . . 78
Pin mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
Hysteresis . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
GPIO data register . . . . . . . . . . . . . . . . . . . . 120
GPIO data direction register . . . . . . . . . . . . . 121
GPIO interrupt sense register . . . . . . . . . . . . 121
GPIO interrupt both edges sense register . . 122
GPIO interrupt event register . . . . . . . . . . . . 122
GPIO interrupt mask register . . . . . . . . . . . . 122
. . . . Interrupt Set-Enable Register 0 register 58
. . . . . . . . . . . Interrupt Set-Enable Register 1 59
. . . Interrupt Clear-Enable Register 1 register 61
. . . . Interrupt Set-Pending Register 0 register 62
. . . . Interrupt Set-Pending Register 1 register 63
. . Interrupt Clear-Pending Register 0 register 64
. . Interrupt Clear-Pending Register 1 register 66
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 7 July 2010
3.10.4.1
3.10.4.2
3.11
4.2.2
4.2.3
4.3
5.6.10
5.6.11
5.6.12
5.6.13
5.6.14
5.6.15
5.6.16
5.6.17
5.6.18
5.6.19
5.6.20
5.6.21
5.6.22
5.6.23
5.6.24
5.6.25
5.6.26
6.3.4
6.3.5
6.4
6.4.1
6.4.1.1
7.4
7.4.1
7.4.2
8.4.7
8.4.8
8.4.9
8.5
8.5.1
Chapter 21: LPC13xx Supplementary information
Flash memory access. . . . . . . . . . . . . . . . . . . 50
Functional description . . . . . . . . . . . . . . . . . . 52
Register description . . . . . . . . . . . . . . . . . . . . 79
Pin description . . . . . . . . . . . . . . . . . . . . . . . . 112
Functional description . . . . . . . . . . . . . . . . . 124
Normal mode . . . . . . . . . . . . . . . . . . . . . . . . . 49
Power-down mode . . . . . . . . . . . . . . . . . . . . . 50
General purpose registers 0 to 3 . . . . . . . . . 52
General purpose register 4 . . . . . . . . . . . . . . 52
Interrupt Active Bit Register 1 . . . . . . . . . . . . 68
Interrupt Priority Register 0 . . . . . . . . . . . . . . 69
Interrupt Priority Register 1 . . . . . . . . . . . . . . 69
Interrupt Priority Register 2 . . . . . . . . . . . . . . 70
Interrupt Priority Register 3 . . . . . . . . . . . . . . 70
Interrupt Priority Register 4 . . . . . . . . . . . . . . 71
Interrupt Priority Register 5 . . . . . . . . . . . . . . 71
Interrupt Priority Register 6 . . . . . . . . . . . . . . 72
Interrupt Priority Register 7 . . . . . . . . . . . . . . 72
Interrupt Priority Register 8 . . . . . . . . . . . . . . 73
Interrupt Priority Register 9 . . . . . . . . . . . . . . 73
Interrupt Priority Register 10 . . . . . . . . . . . . . 74
Interrupt Priority Register 11 . . . . . . . . . . . . . 74
Interrupt Priority Register 12 . . . . . . . . . . . . . 75
Interrupt Priority Register 13 . . . . . . . . . . . . . 75
Interrupt Priority Register 14 . . . . . . . . . . . . . 76
Software Trigger Interrupt Register . . . . . . . . 76
A/D-mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
I
I/O configuration registers IOCON_PIOn. . . . 82
IOCON SCK location register . . . . . . . . . . . 106
LQFP48 packages . . . . . . . . . . . . . . . . . . . . . 113
HVQFN33 packages . . . . . . . . . . . . . . . . . . . 116
GPIO raw interrupt status register . . . . . . . . 122
GPIO masked interrupt status register. . . . . 123
GPIO interrupt clear register . . . . . . . . . . . . 123
Write/read data operations. . . . . . . . . . . . . . 124
Write operation. . . . . . . . . . . . . . . . . . . . . . . . 124
Read operation . . . . . . . . . . . . . . . . . . . . . . . 125
2
C mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
UM10375
© NXP B.V. 2010. All rights reserved.
327 of 333
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