LPC1343FHN33,551 NXP Semiconductors, LPC1343FHN33,551 Datasheet - Page 235
LPC1343FHN33,551
Manufacturer Part Number
LPC1343FHN33,551
Description
IC MCU 32BIT 32KB FLASH 33HVQFN
Manufacturer
NXP Semiconductors
Series
LPC13xxr
Specifications of LPC1343FHN33,551
Program Memory Type
FLASH
Program Memory Size
32KB (32K x 8)
Package / Case
33-VQFN Exposed Pad, 33-HVQFN, 33-SQFN, 33-DHVQFN
Core Processor
ARM® Cortex-M3™
Core Size
32-Bit
Speed
72MHz
Connectivity
I²C, Microwire, SPI, SSI, SSP, UART/USART, USB
Peripherals
Brown-out Detect/Reset, POR, WDT
Number Of I /o
28
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
2 V ~ 3.6 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
LPC13
Core
ARM Cortex M3
Data Bus Width
32 bit
Data Ram Size
8 KB
Interface Type
I2C, UART
Maximum Clock Frequency
72 MHz
Number Of Programmable I/os
28
Number Of Timers
4
Operating Supply Voltage
3.3 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2, KSK-LPC1343
Development Tools By Supplier
OM11039, OM11040, OM11046, OM11048
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 8 Channel
Package
33HVQFN EP
Device Core
ARM Cortex M3
Family Name
LPC1000
Maximum Speed
72 MHz
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
568-4944
935289655551
935289655551
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LPC1343FHN33,551
Manufacturer:
NXP
Quantity:
780
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NXP Semiconductors
13.6 Clocking and power control
13.7 Register description
UM10375
User manual
The clocks and power to the SSP block are controlled by two registers:
Remark: Before accessing the SSP block, ensure that the SSP_RST_N bit (bit 0) in the
PRESETCTRL register
block.
The register addresses of the SSP controller are shown in
Table 234. Register overview: SSP (base address 0x4004 0000)
[1]
Name
SSP0CR0
SSP0CR1
SSP0DR
SSP0SR
SSP0CPSR
SSP0IMSC
SSP0RIS
SSP0MIS
SSP0ICR
1. The SSP block can be enabled or disabled through the SYSAHBCLKCTRL register
2. The SSP_PCLK is enabled in the SSP clock divider register (see
(see
is used by the SSP clock prescaler
Reset value reflects the data stored in used bits only. It does not include reserved bits content.
Table
23).
All information provided in this document is subject to legal disclaimers.
Access Address
R/W
R/W
R/W
RO
R/W
R/W
RO
RO
WO
(Table
Rev. 2 — 7 July 2010
offset
0x000
0x004
0x008
0x00C
0x010
0x014
0x018
0x01C
0x020
7) is set to 1. This de-asserts the reset signal to the SSP
Description
Control Register 0. Selects the serial clock rate,
bus type, and data size.
Control Register 1. Selects master/slave and
other modes.
Data Register. Writes fill the transmit FIFO, and
reads empty the receive FIFO.
Status Register.
Clock Prescale Register.
Interrupt Mask Set and Clear Register.
Raw Interrupt Status Register.
Masked Interrupt Status Register.
SSPICR Interrupt Clear Register.
(Table
239).
Table
Chapter 13: LPC13xx SSP
234.
Table
UM10375
© NXP B.V. 2010. All rights reserved.
24). This clock
Reset
value
0
0
0
0x0000
0003
0
0
0x0000
0008
0
NA
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