LPC1343FHN33,551 NXP Semiconductors, LPC1343FHN33,551 Datasheet - Page 190

• Manufacturer Part Number: LPC1343FHN33,551
• Description: IC MCU 32BIT 32KB FLASH 33HVQFN
• Manufacturer: NXP Semiconductors
• Series: LPC13xxr

Specifications of LPC1343FHN33,551

• Program Memory Type: FLASH
• Program Memory Size: 32KB (32K x 8)
• Package / Case: 33-VQFN Exposed Pad, 33-HVQFN, 33-SQFN, 33-DHVQFN
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 72MHz
• Connectivity: I²C, Microwire, SPI, SSI, SSP, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, POR, WDT
• Number Of I /o: 28
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: LPC13
• Core: ARM Cortex M3
• Data Bus Width: 32 bit
• Data Ram Size: 8 KB
• Interface Type: I2C, UART
• Maximum Clock Frequency: 72 MHz
• Number Of Programmable I/os: 28
• Number Of Timers: 4
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2, KSK-LPC1343
• Development Tools By Supplier: OM11039, OM11040, OM11046, OM11048
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• Package: 33HVQFN EP
• Device Core: ARM Cortex M3
• Family Name: LPC1000
• Maximum Speed: 72 MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-4944; 935289655551

12.1 How to read this chapter
12.2 Basic configuration
12.3 Features
12.4 Applications
12.5 General description
UM10375
User manual
The I
The I
Interfaces to external I
other microcontrollers, etc.
A typical I
direction bit (R/W), two types of data transfers are possible on the I
1. Pins: The I2C pin functions and the I2C mode are configured in the IOCONFIG
2. Power and peripheral clock: In the SYSAHBCLKCTRL register, set bit 5
3. Reset: Before accessing the I2C block, ensure that the I2C_RST_N bit (bit 1) in the
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UM10375
Chapter 12: LPC13xx I2C-bus controller
Rev. 2 — 7 July 2010
register block
PRESETCTRL register
block.
Standard I
Master/Slave.
Arbitration is handled between simultaneously transmitting masters without corruption
of serial data on the bus.
Programmable clock allows adjustment of I
Data transfer is bidirectional between masters and slaves.
Serial clock synchronization allows devices with different bit rates to communicate via
one serial bus.
Serial clock synchronization is used as a handshake mechanism to suspend and
resume serial transfer.
Supports Fast-mode Plus.
Optional recognition of up to four distinct slave addresses.
Monitor mode allows observing all I
I
The I
2
2
2
C-bus can be used for test and diagnostic purposes.
C-bus block is identical for all LPC13xx parts.
C-bus interface is configured using the following registers:
2
2
C-bus contains a standard I
C-bus configuration is shown in
2
C-compliant bus interfaces may be configured as Master, Slave, or
All information provided in this document is subject to legal disclaimers.
(Table 102
2
C standard parts, such as serial RAMs, LCDs, tone generators,
Rev. 2 — 7 July 2010
(Table
and
Table
7) is set to 1. This de-asserts the reset signal to the I2C
2
C-compliant bus interface with two pins.
2
103).
C-bus traffic, regardless of slave address.
Figure
2
C transfer rates.
21. Depending on the state of the
2
C-bus:
© NXP B.V. 2010. All rights reserved.
User manual
(Table
192 of 333
23).