LPC1343FHN33,551 NXP Semiconductors, LPC1343FHN33,551 Datasheet - Page 25

• Manufacturer Part Number: LPC1343FHN33,551
• Description: IC MCU 32BIT 32KB FLASH 33HVQFN
• Manufacturer: NXP Semiconductors
• Series: LPC13xxr

Specifications of LPC1343FHN33,551

• Program Memory Type: FLASH
• Program Memory Size: 32KB (32K x 8)
• Package / Case: 33-VQFN Exposed Pad, 33-HVQFN, 33-SQFN, 33-DHVQFN
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 72MHz
• Connectivity: I²C, Microwire, SPI, SSI, SSP, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, POR, WDT
• Number Of I /o: 28
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: LPC13
• Core: ARM Cortex M3
• Data Bus Width: 32 bit
• Data Ram Size: 8 KB
• Interface Type: I2C, UART
• Maximum Clock Frequency: 72 MHz
• Number Of Programmable I/os: 28
• Number Of Timers: 4
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2, KSK-LPC1343
• Development Tools By Supplier: OM11039, OM11040, OM11046, OM11048
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• Package: 33HVQFN EP
• Device Core: ARM Cortex M3
• Family Name: LPC1000
• Maximum Speed: 72 MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-4944; 935289655551

NXP Semiconductors
UM10375
User manual
3.5.19 SSP clock divider register
3.5.20 UART clock divider register
Table 23.
This register configures the SSP peripheral clock SSP_PCLK. The SSP_PCLK can be
shut down by setting the DIV bits to 0x0.
Table 24.
This register configures the UART peripheral clock UART_PCLK. The UART_PCLK can
be shut down by setting the DIV bits to 0x0.
Remark: Note that the UART pins must be configured in the IOCON block before the
UART clock can be enabled.
Table 25.
Bit
14
15
16
31:17
Bit
7:0
31:8
Bit
7:0
31:8
Symbol
USB_REG
WDT
IOCON
-
Symbol
DIV
-
Symbol
DIV
-
System AHB clock control register (SYSAHBCLKCTRL, address 0x4004 8080) bit
description
UART clock divider register (UARTCLKDIV, address 0x4004 8098) bit description
SSP clock divider register (SSPCLKDIV, address 0x4004 8094) bit description
All information provided in this document is subject to legal disclaimers.
Value
0
1
to
255
Value
0
1
to
255
-
-
…continued
Value
0
1
0
1
0
1
-
Rev. 2 — 7 July 2010
Description
SSP_PCLK clock divider values
Disable SSP_PCLK.
Divide by 1.
...
Divide by 255.
Reserved
Description
UART_PCLK clock divider values
Disable UART_PCLK.
Divide by 1.
...
Divide by 255.
Reserved
Description
Enables clock for USB_REG.
Disabled
Enabled
Enables clock for WDT.
Disabled
Enabled
Enables clock for IO configuration block.
Disabled
Enabled
Reserved
Chapter 3: LPC13xx System configuration
UM10375
© NXP B.V. 2010. All rights reserved.
Reset
value
1
0
0
0x00
26 of 333
Reset
value
0x01
0x00
Reset
value
0x00
0x00