LPC1343FHN33,551 NXP Semiconductors, LPC1343FHN33,551 Datasheet - Page 330

• Manufacturer Part Number: LPC1343FHN33,551
• Description: IC MCU 32BIT 32KB FLASH 33HVQFN
• Manufacturer: NXP Semiconductors
• Series: LPC13xxr

Specifications of LPC1343FHN33,551

• Program Memory Type: FLASH
• Program Memory Size: 32KB (32K x 8)
• Package / Case: 33-VQFN Exposed Pad, 33-HVQFN, 33-SQFN, 33-DHVQFN
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 72MHz
• Connectivity: I²C, Microwire, SPI, SSI, SSP, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, POR, WDT
• Number Of I /o: 28
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: LPC13
• Core: ARM Cortex M3
• Data Bus Width: 32 bit
• Data Ram Size: 8 KB
• Interface Type: I2C, UART
• Maximum Clock Frequency: 72 MHz
• Number Of Programmable I/os: 28
• Number Of Timers: 4
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2, KSK-LPC1343
• Development Tools By Supplier: OM11039, OM11040, OM11046, OM11048
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• Package: 33HVQFN EP
• Device Core: ARM Cortex M3
• Family Name: LPC1000
• Maximum Speed: 72 MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-4944; 935289655551

NXP Semiconductors
Chapter 16: LPC13xx System tick timer
16.1
16.2
16.3
16.4
16.5
16.6
16.6.1
Chapter 17: LPC13xx WatchDog Timer (WDT)
17.1
17.2
17.3
17.4
17.5
17.6
17.7
Chapter 18: LPC13xx Analog-to-Digital Converter (ADC)
18.1
18.2
18.3
18.4
18.5
18.6
18.6.1
18.6.2
Chapter 19: LPC13xx Flash memory programming firmware
19.1
19.2
19.2.1
19.3
19.4
19.5
19.6
19.7
19.8
19.8.1
19.8.2
19.8.3
19.8.4
19.8.5
19.8.6
19.8.7
19.8.8
UM10375
User manual
How to read this chapter . . . . . . . . . . . . . . . . 274
Basic configuration . . . . . . . . . . . . . . . . . . . . 274
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 274
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . 274
Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 275
Register description . . . . . . . . . . . . . . . . . . . 275
How to read this chapter . . . . . . . . . . . . . . . . 279
Basic configuration . . . . . . . . . . . . . . . . . . . . 279
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 279
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . 279
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . 280
Clocking and power control . . . . . . . . . . . . . 280
Register description . . . . . . . . . . . . . . . . . . . 280
How to read this chapter . . . . . . . . . . . . . . . . 284
Basic configuration . . . . . . . . . . . . . . . . . . . . 284
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 284
Pin description . . . . . . . . . . . . . . . . . . . . . . . . 284
Clocking and power control . . . . . . . . . . . . . 285
Register description . . . . . . . . . . . . . . . . . . . 285
How to read this chapter . . . . . . . . . . . . . . . . 290
Bootloader . . . . . . . . . . . . . . . . . . . . . . . . . . . 290
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 291
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . 291
Memory map after any reset . . . . . . . . . . . . . 292
Flash content protection mechanism . . . . . 292
Criterion for Valid User Code . . . . . . . . . . . . 292
ISP/IAP communication protocol . . . . . . . . . 293
System Timer Control and status register (CTRL -
0xE000 E010) . . . . . . . . . . . . . . . . . . . . . . . . 276
A/D Control Register (AD0CR - 0x4001
C000) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 286
A/D Global Data Register (AD0GDR -
0x4001 C004) . . . . . . . . . . . . . . . . . . . . . . . . 287
Bootloader code version 5.2 notes . . . . . . . . 290
ISP command format . . . . . . . . . . . . . . . . . . 293
ISP response format . . . . . . . . . . . . . . . . . . . 293
ISP data format. . . . . . . . . . . . . . . . . . . . . . . 293
ISP flow control. . . . . . . . . . . . . . . . . . . . . . . 294
ISP command abort . . . . . . . . . . . . . . . . . . . 294
Interrupts during ISP. . . . . . . . . . . . . . . . . . . 294
Interrupts during IAP. . . . . . . . . . . . . . . . . . . 294
RAM used by ISP command handler . . . . . . 294
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 7 July 2010
16.6.2
16.6.3
16.6.4
16.7
17.7.1
17.7.2
17.7.3
17.7.4
17.8
18.6.3
18.6.4
18.6.5
18.7
18.7.1
18.7.2
19.8.9
19.9
19.9.1
19.10
19.11
19.12
19.12.1
19.13
19.13.1
19.13.2
19.13.3
19.13.4
19.13.5
19.13.6
Chapter 21: LPC13xx Supplementary information
Example timer calculations . . . . . . . . . . . . . 278
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . 283
Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 289
USB communication protocol . . . . . . . . . . . 294
Boot process flowchart . . . . . . . . . . . . . . . . 296
Sector numbers. . . . . . . . . . . . . . . . . . . . . . . 297
Code Read Protection (CRP) . . . . . . . . . . . . 297
ISP commands . . . . . . . . . . . . . . . . . . . . . . . 300
System Timer Reload value register (LOAD -
0xE000 E014) . . . . . . . . . . . . . . . . . . . . . . . 276
System Timer Current value register (VAL -
0xE000 E018) . . . . . . . . . . . . . . . . . . . . . . . 276
System Timer Calibration value register (CALIB -
0xE000 E01C) . . . . . . . . . . . . . . . . . . . . . . . 277
System clock = 72 MHz . . . . . . . . . . . . . . . . . 278
System tick timer clock = 24 MHz . . . . . . . . . 278
System clock = 12 MHz . . . . . . . . . . . . . . . . . 278
Watchdog Mode register (WDMOD -
0x4000 0000) . . . . . . . . . . . . . . . . . . . . . . . . 281
Watchdog Timer Constant register (WDTC -
0x4000 4004) . . . . . . . . . . . . . . . . . . . . . . . . 282
Watchdog Feed register (WDFEED -
0x4000 4008) . . . . . . . . . . . . . . . . . . . . . . . . 282
Watchdog Timer Value register (WDTV -
0x4000 400C) . . . . . . . . . . . . . . . . . . . . . . . 282
A/D Status Register (AD0STAT - 0x4001 C030) .
288
A/D Interrupt Enable Register (AD0INTEN -
0x4001 C00C) . . . . . . . . . . . . . . . . . . . . . . . 288
A/D Data Registers (AD0DR0 to AD0DR7 -
0x4001 C010 to 0x4001 C02C) . . . . . . . . . . 288
Hardware-triggered conversion . . . . . . . . . . 289
Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . 289
RAM used by IAP command handler. . . . . . 294
Usage note. . . . . . . . . . . . . . . . . . . . . . . . . . 295
ISP entry protection . . . . . . . . . . . . . . . . . . . 299
Unlock <Unlock code> . . . . . . . . . . . . . . . . . 300
Set Baud Rate <Baud Rate> <stop bit>. . . . 301
Echo <setting> . . . . . . . . . . . . . . . . . . . . . . . 301
Write to RAM <start address>
<number of bytes> . . . . . . . . . . . . . . . . . . . . 301
Read Memory <address> <no. of bytes>. . . 302
Prepare sector(s) for write operation <start sector
number> <end sector number> . . . . . . . . . . 302
UM10375
© NXP B.V. 2010. All rights reserved.
332 of 333