LPC1343FHN33,551 NXP Semiconductors, LPC1343FHN33,551 Datasheet - Page 211
LPC1343FHN33,551
Manufacturer Part Number
LPC1343FHN33,551
Description
IC MCU 32BIT 32KB FLASH 33HVQFN
Manufacturer
NXP Semiconductors
Series
LPC13xxr
Specifications of LPC1343FHN33,551
Program Memory Type
FLASH
Program Memory Size
32KB (32K x 8)
Package / Case
33-VQFN Exposed Pad, 33-HVQFN, 33-SQFN, 33-DHVQFN
Core Processor
ARM® Cortex-M3™
Core Size
32-Bit
Speed
72MHz
Connectivity
I²C, Microwire, SPI, SSI, SSP, UART/USART, USB
Peripherals
Brown-out Detect/Reset, POR, WDT
Number Of I /o
28
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
2 V ~ 3.6 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
LPC13
Core
ARM Cortex M3
Data Bus Width
32 bit
Data Ram Size
8 KB
Interface Type
I2C, UART
Maximum Clock Frequency
72 MHz
Number Of Programmable I/os
28
Number Of Timers
4
Operating Supply Voltage
3.3 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2, KSK-LPC1343
Development Tools By Supplier
OM11039, OM11040, OM11046, OM11048
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 8 Channel
Package
33HVQFN EP
Device Core
ARM Cortex M3
Family Name
LPC1000
Maximum Speed
72 MHz
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
568-4944
935289655551
935289655551
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LPC1343FHN33,551
Manufacturer:
NXP
Quantity:
780
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NXP Semiconductors
UM10375
User manual
Fig 30. Format and states in the Master Transmitter mode
successful
transmission
to a Slave
Receiver
next transfer
started with a
Repeated Start
condition
Not
Acknowledge
received after
the Slave
address
Not
Acknowledge
received after a
Data byte
arbitration lost
in Slave
address or
Data byte
arbitration lost
and
addressed as
Slave
DATA
n
08H
from Master to Slave
from Slave to Master
S
any number of data bytes and their associated Acknowledge bits
this number (contained in I2STA) corresponds to a defined state of the
I
2
C bus
SLA
All information provided in this document is subject to legal disclaimers.
W
MT
A OR A
18H
20H
68H 78H B0H
A
A
A
38H
Rev. 2 — 7 July 2010
P
other Master
continues
other Master
continues
DATA
states in Slave mode
to corresponding
Chapter 12: LPC13xx I2C-bus controller
A OR A
28H
30H
A
A
38H
10H
P
S
P
other Master
continues
SLA
to Master
receive
UM10375
mode,
= MR
entry
© NXP B.V. 2010. All rights reserved.
W
R
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