LPC1343FHN33,551 NXP Semiconductors, LPC1343FHN33,551 Datasheet - Page 37

• Manufacturer Part Number: LPC1343FHN33,551
• Description: IC MCU 32BIT 32KB FLASH 33HVQFN
• Manufacturer: NXP Semiconductors
• Series: LPC13xxr

Specifications of LPC1343FHN33,551

• Program Memory Type: FLASH
• Program Memory Size: 32KB (32K x 8)
• Package / Case: 33-VQFN Exposed Pad, 33-HVQFN, 33-SQFN, 33-DHVQFN
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 72MHz
• Connectivity: I²C, Microwire, SPI, SSI, SSP, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, POR, WDT
• Number Of I /o: 28
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: LPC13
• Core: ARM Cortex M3
• Data Bus Width: 32 bit
• Data Ram Size: 8 KB
• Interface Type: I2C, UART
• Maximum Clock Frequency: 72 MHz
• Number Of Programmable I/os: 28
• Number Of Timers: 4
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2, KSK-LPC1343
• Development Tools By Supplier: OM11039, OM11040, OM11046, OM11048
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• Package: 33HVQFN EP
• Device Core: ARM Cortex M3
• Family Name: LPC1000
• Maximum Speed: 72 MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-4944; 935289655551

NXP Semiconductors
UM10375
User manual
3.5.44 Deep-sleep mode configuration register
This register controls the behavior of the WatchDog (WD) oscillator and the BOD circuit
when the device enters Deep-sleep mode.
This register must be initialized at least once before entering Deep-sleep mode with
one of the four values shown in
Table 49.
Remark: Failure to initialize and program this register correctly may result in undefined
behavior of the microcontroller. The values listed in
for PDSLEEPCFG register.
To select the appropriate power configuration for Deep-sleep mode, consider the
following:
Remark: Reserved bits in this register must always be written as indicated. This register
must be initialized correctly before entering Deep-sleep mode.
Table 50.
Configuration
BOD on
BOD off
Bit
2:0
3
5:4
•
•
BOD: Leaving the BOD circuit enabled will protect the part from a low voltage event
occurring while the part is in Deep-sleep mode. However, the BOD circuit causes an
WD oscillator: The watchdog oscillator can be left running in Deep-sleep mode to
provide a clock for the watchdog timer or a general purpose timer if they are needed
for timing a wake-up event (see
oscillator analog output frequency must be set to its lowest value (bits FREQSEL in
the WDTOSCCTRL = 0001, see
timer clock must be disabled in the SYSAHBCLKCTRL register (see
entering Deep-sleep mode.
The watchdog oscillator, if running, contributes an additional current drain in
Deep-sleep mode.
additional current drain in Deep-sleep mode.
Symbol
-
BOD_PD
-
Allowed values for PDSLEEPCFG register
description
Deep-sleep configuration register (PDSLEEPCFG, address 0x4004 8230) bit
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 7 July 2010
Value
111
0
1
11
WD oscillator on
PDSLEEPCFG = 0x0000 0FB7 PDSLEEPCFG = 0x0000 0FF7
PDSLEEPCFG = 0x0000 0FBF PDSLEEPCFG = 0x0000 0FFF
Table
Description
Reserved. Always write these bits as 111.
BOD power-down control in Deep-sleep mode, see
Table
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Reserved. Always write these bits as 11.
Section 3.9.3
Table
49:
49.
13) and all peripheral clocks other than the
Chapter 3: LPC13xx System configuration
for details). In this case, the watchdog
Table 49
WD oscillator off
are the only values allowed
UM10375
© NXP B.V. 2010. All rights reserved.
Table
23) before
38 of 333
Reset
value
0
0
0