LPC1343FHN33,551 NXP Semiconductors, LPC1343FHN33,551 Datasheet - Page 249
LPC1343FHN33,551
Manufacturer Part Number
LPC1343FHN33,551
Description
IC MCU 32BIT 32KB FLASH 33HVQFN
Manufacturer
NXP Semiconductors
Series
LPC13xxr
Specifications of LPC1343FHN33,551
Program Memory Type
FLASH
Program Memory Size
32KB (32K x 8)
Package / Case
33-VQFN Exposed Pad, 33-HVQFN, 33-SQFN, 33-DHVQFN
Core Processor
ARM® Cortex-M3™
Core Size
32-Bit
Speed
72MHz
Connectivity
I²C, Microwire, SPI, SSI, SSP, UART/USART, USB
Peripherals
Brown-out Detect/Reset, POR, WDT
Number Of I /o
28
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
2 V ~ 3.6 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
LPC13
Core
ARM Cortex M3
Data Bus Width
32 bit
Data Ram Size
8 KB
Interface Type
I2C, UART
Maximum Clock Frequency
72 MHz
Number Of Programmable I/os
28
Number Of Timers
4
Operating Supply Voltage
3.3 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2, KSK-LPC1343
Development Tools By Supplier
OM11039, OM11040, OM11046, OM11048
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 8 Channel
Package
33HVQFN EP
Device Core
ARM Cortex M3
Family Name
LPC1000
Maximum Speed
72 MHz
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
568-4944
935289655551
935289655551
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LPC1343FHN33,551
Manufacturer:
NXP
Quantity:
780
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14.5 Description
14.6 Pin description
Table 244. Counter/timer pin description
14.7 Clocking and power control
14.8 Register description
UM10375
User manual
Pin
CT16B0_CAP0
CT16B1_CAP0
CT16B0_MAT[2:0]
CT16B1_MAT[1:0]
Each Counter/timer is designed to count cycles of the peripheral clock (PCLK) or an
externally supplied clock and can optionally generate interrupts or perform other actions at
specified timer values based on four match registers. Each counter/timer also includes
one capture input to trap the timer value when an input signal transitions, optionally
generating an interrupt.
In PWM mode, three match registers on CT16B0 and two match registers on CT16B1 can
be used to provide a single-edge controlled PWM output on the match output pins. It is
recommended to use the match registers that are not pinned out to control the PWM cycle
length.
Remark: The 16-bit counter/timer0 (CT16B0) and the 16-bit counter/timer1 (CT16B1) are
functionally identical except for the peripheral base address.
Table 244
The peripheral clocks (PCLK) to the 16-bit timers are provided by the system clock (see
Figure
register
The 16-bit counter/timer0 contains the registers shown in
counter/timer1 contains the registers shown in
follow.
Type
Input
Output
3). These clocks can be disabled through bit 7 and 8 in the SYSAHBCLKCTRL
(Table
gives a brief summary of each of the counter/timer related pins.
Description
Capture Signal:
A transition on a capture pin can be configured to load the Capture Register with the
value in the counter/timer and optionally generate an interrupt.
Counter/Timer block can select a capture signal as a clock source instead of the PCLK
derived clock. For more details see
External Match Outputs of CT16B0/1:
When a match register of CT16B0/1 (MR3:0) equals the timer counter (TC), this output
can either toggle, go LOW, go HIGH, or do nothing. The External Match Register
(EMR) and the PWM Control Register (PWMCON) control the functionality of this
output.
23) for power savings.
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 7 July 2010
Chapter 14: LPC13xx 16-bit timer/counters (CT16B0/1)
Section
Table
14.8.11.
246. More detailed descriptions
Table 245
and the 16-bit
UM10375
© NXP B.V. 2010. All rights reserved.
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